<urlset xmlns="http://www.sitemaps.org/schemas/sitemap/0.9" xmlns:xhtml="http://www.w3.org/1999/xhtml"><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/00-Index</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/01-Fundamentals</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy/01-Cache</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy/02-Virtual-Memory</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy/03-Memory-Tech</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy/04-Optimizations</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy/05-Protection</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy/06-Cross-Cutting-Issues</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy/07-Cortex-A53</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy/08-Intel-Core-i9-12900</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/02-Memory-Hierarchy/XX-Cache-and-VM-Lab</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/01-Pipelining</loc>
    <lastmod>2026-04-19T12:04:41.768Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/02-ILP</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/03-Compiler-ILP</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/04-Superscalar</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/05-Branch-Prediction</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/06-Register-Renaming</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/07-Dynamic-Scheduling</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/08-Dynamic-Disambiguation</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/09-Advanced-Issues</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/10-Multiple-Issue</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/11-Cross-Cutting-Issues</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/12-Multithreading</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/13-Side-Channel-Attacks</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/14-Cortex-53</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/03-Instruction-Level-Parallelism/15-Intel-Golden-Clove</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/00-Introduction</loc>
    <lastmod>2026-04-19T12:04:41.769Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/01-Vector-Architecture</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/02-SIMD-Extensions</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/03-GPU-Architecture</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/04-Loop-Level-Parallelism</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/05-Cross-Cutting-Issues</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/06-Tesla-vs-Core-i7</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/00-Introduction</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/01-Cache-Coherence</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/02-Snooping</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/03-Directory</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/04-Synchronization</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/05-Memory-Consistency</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/06-Cross-Cutting-Issues</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/07-Multicore-Performance</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/06-Warehouse-Scale-Architectures</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/06-Warehouse-Scale-Architectures/00-Introduction</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/06-Warehouse-Scale-Architectures/01-Cloud-Computing</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/06-Warehouse-Scale-Architectures/02-Virtualization</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/06-Warehouse-Scale-Architectures/03-WSC-Architecture</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/06-Warehouse-Scale-Architectures/04-IO-Devices</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/06-Warehouse-Scale-Architectures/05-Power-and-Cooling</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/06-Warehouse-Scale-Architectures/06-Cost-and-Efficiency</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/06-Warehouse-Scale-Architectures/07-Custom-Silicon-in-AWS-Cloud</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/07-Domain-Specific-Architectures</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/Storage-Systems</loc>
    <lastmod>2026-04-19T12:04:41.770Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/Linux/Three-Easy-Pieces/00-Index</loc>
    <lastmod>2026-04-19T12:04:41.771Z</lastmod>
  </url><url>
    <loc>https://my-knowledge-base-bmo.pages.dev/</loc>
    <lastmod>2026-04-19T12:04:41.771Z</lastmod>
  </url></urlset>