<?xml version="1.0" encoding="UTF-8" ?>
<rss version="2.0">
    <channel>
      <title>My Knowledge Base</title>
      <link>https://my-knowledge-base-bmo.pages.dev</link>
      <description>Last 10 notes on My Knowledge Base</description>
      <generator>Quartz -- quartz.jzhao.xyz</generator>
      <item>
    <title>00 Index</title>
    <link>https://my-knowledge-base-bmo.pages.dev/Linux/Three-Easy-Pieces/00-Index</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/Linux/Three-Easy-Pieces/00-Index</guid>
    <description><![CDATA[ Operating Systems: Three Easy Pieces Book 01 Introduction.pdf 02 Virtualization.pdf 03 Concurrency.pdf 04 Persistence and Distribution.pdf. ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item><item>
    <title>Reading Notes</title>
    <link>https://my-knowledge-base-bmo.pages.dev/</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/</guid>
    <description><![CDATA[ Reading Notes Computer Architecture. ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item><item>
    <title>01 Vector Architecture</title>
    <link>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/01-Vector-Architecture</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/01-Vector-Architecture</guid>
    <description><![CDATA[ Vector Architecture Vector architectures grab sets of data elements scattered throughout memory, place them into large sequential register files, operate on them using deep pipelines, and disperse the results back to memory. ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item><item>
    <title>02 SIMD Extensions</title>
    <link>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/02-SIMD-Extensions</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/02-SIMD-Extensions</guid>
    <description><![CDATA[ SIMD Instruction Set Extensions for Multimedia Core Mechanics and Hardware Implementation Fundamental Principle: Media applications frequently operate on narrow data types, such as 8-bit values for color and transparency or 16-bit values for audio samples. ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item><item>
    <title>03 GPU Architecture</title>
    <link>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/03-GPU-Architecture</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/03-GPU-Architecture</guid>
    <description><![CDATA[ Graphics Processing Units (GPUs) Graphics Processing Units (GPUs) are highly parallel, affordable computing devices consisting of thousands of floating-point units. ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item><item>
    <title>04 Loop-Level Parallelism</title>
    <link>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/04-Loop-Level-Parallelism</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/04-Loop-Level-Parallelism</guid>
    <description><![CDATA[ Detecting and Enhancing Loop-Level Parallelism 1. ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item><item>
    <title>05 Cross-Cutting Issues</title>
    <link>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/05-Cross-Cutting-Issues</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/05-Cross-Cutting-Issues</guid>
    <description><![CDATA[ Cross-Cutting Issues in Data-Level Parallelism Energy and Data-Level Parallelism: Slow and Wide Versus Fast and Narrow Data-level parallel architectures possess a fundamental power advantage derived from core system energy equations. ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item><item>
    <title>06 Tesla vs Core i7</title>
    <link>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/06-Tesla-vs-Core-i7</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/04-Data-Level-Parallelism/06-Tesla-vs-Core-i7</guid>
    <description><![CDATA[ Hardware Specifications and Roofline Limits Processor Architecture and Capabilities: Intel Core i7-960: Manufactured on a 45 nm process, containing 4 cores and 700 million transistors, running at 3.2 GHz with a 130W power envelope. ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item><item>
    <title>05 Thread-Level Parallelism</title>
    <link>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism</guid>
    <description><![CDATA[ Thread-Level Parallelism Source: 05 Thread Level Parallelism.pdf Note map 00 Introduction 01 Cache Coherence 02 Snooping 03 Directory 04 Synchronization 05 Memory Consistency 06 Cross-Cutting Issues 07 Multicore Performance . ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item><item>
    <title>00 Introduction</title>
    <link>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/00-Introduction</link>
    <guid>https://my-knowledge-base-bmo.pages.dev/Computer-Architecture/CAQA/05-Thread-Level-Parallelism/00-Introduction</guid>
    <description><![CDATA[ Introduction to Thread-Level Parallelism Drivers of Multiprocessing and Thread-Level Parallelism Multiprocessing has become the primary mechanism to scale computational performance due to physical limitations in scaling single-core architectures. ]]></description>
    <pubDate>Sun, 19 Apr 2026 12:04:41 GMT</pubDate>
  </item>
    </channel>
  </rss>