02 RV32I

RV32I: RISC-V Base Integer ISA

The RV32I base instruction set architecture provides the foundational 32-bit execution environment upon which all other RISC-V extensions are built. It defines the core data formats, registers, memory interactions, and control flow mechanisms required to run a full software stack.

Uniform instruction decoding relies heavily on the structured placement of bits within a constrained set of formats.

Instruction Formats

The RV32I ISA utilizes exactly six 32-bit instruction formats: R-type, I-type, S-type, B-type, U-type, and J-type. All instructions are 32 bits long, eliminating the decode complexity associated with byte-variable instruction lengths.

• R-type: Register-to-register operations.
• I-type: Short immediates and load operations.
• S-type: Store operations.
• B-type: Conditional branches, fundamentally a variation of the S-type where the immediate field is rotated by 1 bit.
• U-type: Long immediates.
• J-type: Unconditional jumps, fundamentally a variation of the U-type where the immediate field is rotated by 12 bits.

Core design principles applied across these formats minimize implementation complexity:

• Three Register Operands: Instructions independently specify two source registers and one destination register, preventing the need for supplementary move instructions.
• Fixed Register Specifiers: Register read and write specifiers occupy identical bit positions across all formats. This enables register access to begin before instruction decoding completes.
• Sign-Extended Immediates: Immediate fields are universally sign-extended, and the sign bit constantly occupies the most significant bit (bit 31) of the instruction word. Immediate sign extension proceeds parallel to instruction decode.
• Rotated Immediates: Bit placement within immediate operands is rotated from natural ordering to reduce instruction signal fanout and hardware multiplexing costs.
• Trap Patterns: An instruction bit pattern of all zeros or all ones constitutes an illegal instruction, immediately trapping out-of-bounds jumps or unprogrammed memory accesses.

The predictable placement of register specifiers relies on a universally available, simple set of architected register targets.

Registers

The RV32I base specifies 32 general-purpose integer registers, each 32 bits wide.

• x0 (zero): Hardwired to the constant value 0.
• x1 through x31: General-purpose 32-bit read/write registers.

The Program Counter (PC) is strictly separated from the general-purpose registers. Excluding the PC from general register addressability stabilizes hardware branch prediction by preventing standard arithmetic operations from causing arbitrary control flow side effects.

The inclusion of x0 simplifies the ISA by eliminating the need for dedicated zero-state or unary instructions. Operations like register-to-register moves or arithmetic negations are synthesized by using standard instructions with x0 as a source operand.

These 32 integer registers serve as the exclusive targets and sources for all base arithmetic, logical, and shift operations.

Integer Computation

RV32I integer computation instructions perform full 32-bit register-width operations. Narrow byte or half-word computations are omitted, as they yield no energy savings over full-width operations within the execution datapath.

• Arithmetic Operations: add and sub compute sums and differences. Immediate versions (addi) exist, but an immediate subtract is absent because the sign-extended immediate formats support negative constants.
• Logical Operations: and, or, and xor manipulate bitwise states, accompanied by their respective immediate variants (andi, ori, xori).
• Shift Operations: sll (shift left logical), srl (shift right logical), and sra (shift right arithmetic) slide bits based on register or immediate values.
• Comparison Operations: slt (set less than) compares two registers, writing $1$ to the destination register if the first operand is smaller, and $0$ otherwise. This applies to signed (slt), unsigned (sltu), and immediate forms (slti, sltiu).
• Address and Immediate Generation:
  • lui (load upper immediate) places a 20-bit constant into the uppermost 20 bits of a register.
  • auipc (add upper immediate to PC) loads a 20-bit constant, left-shifted by 12, added to the current PC.
  • Combining lui or auipc with standard 12-bit immediate instructions synthesizes arbitrary 32-bit constants or full 32-bit PC-relative addresses in exactly two instructions.

Integer computation excludes multiply, divide, and integer overflow detection to shrink minimal hardware footprint requirements. Overflow detection is deferred to software branch logic.

Computational results held in registers must eventually be synchronized with memory systems using dedicated transfer operations.

Loads and Stores

Data transfers between registers and memory operate strictly via a single addressing mode: a sign-extended 12-bit immediate added to a base register.

• Word Access: lw (load word) and sw (store word) transfer full 32-bit blocks.
• Partial Access: lb, lh, sb, and sh load and store bytes (8-bit) and halfwords (16-bit).
• Sign and Zero Extension: Narrow loads (lb, lh) sign-extend data to 32 bits before writing to the destination register, ensuring subsequent 32-bit integer computations function safely. Unsigned variants (lbu, lhu) zero-extend the loaded data to 32 bits.

Memory accesses expect data in little-endian byte ordering. Hardware naturally supports unaligned memory accesses via standard load and store instructions, easing porting of legacy code and avoiding specific alignment-assist instructions. RV32I explicitly avoids stack-specific push or pop instructions; stack behavior is fully achieved by utilizing a general register as a stack pointer combined with standard load/store displacement addressing.

Beyond sequential instruction execution and memory manipulation, dynamic program behavior relies on conditional control flow.

Conditional Branching

RV32I evaluates conditional paths by directly comparing two registers without relying on implicit condition codes. Condition codes are excluded because they create implicit dependencies that stall pipelined, out-of-order execution designs.

• Equality: beq (branch equal) and bne (branch not equal).
• Magnitude: blt (branch less than) and bge (branch greater than or equal).
• Unsigned Magnitude: bltu and bgeu explicitly handle unsigned integer comparisons.

Inverse relationships are evaluated by swapping the source operands: $x<y⟹y>x$ $x\ge y⟹y\le x$

Branches utilize PC-relative addressing. The 12-bit immediate is multiplied by 2, sign-extended, and added to the PC, extending the effective branch range while enforcing alignment. Delayed branches, which force execution of the sequentially next instruction regardless of branch outcome, are omitted to prevent architectural binding to historical pipeline lengths.

When logical condition checks are not required, control flow is unconditionally forced to new memory locations.

Unconditional Jumps

Unconditional jumps serve dual purposes: redirecting execution and capturing return addresses for procedure calls.

• Jump and Link (jal): Calculates a target by multiplying its 20-bit immediate by 2, sign-extending it, and adding it to the PC. Simultaneously, it saves the address of the sequentially next instruction (PC+4) into a specified destination register, generally the return address register.
• Jump and Link Register (jalr): Calculates the target dynamically using a base register plus a 12-bit immediate, while saving PC+4 to the destination register.

Standard jump behaviors (without saving a return address) are constructed by assigning the destination of a jal or jalr to x0, securely discarding the link state. jalr combined with x0 acts as a subroutine return mechanism or switch-statement dispatcher.

To supplement computational and control operations, the ISA includes specific administrative functions for the execution environment.

Miscellaneous and System Instructions

Administrative and synchronization tasks interface via system-level RV32I instructions.

• Control Status Registers (CSR): Instructions csrrc, csrrs, csrrw, csrrci, csrrsi, and csrrwi read and manipulate hardware-level counters. These instructions provide read access to 64-bit cycle timers, wall-clock time, and instruction retirement metrics.
• Environment Calls: ecall requests services from the surrounding execution environment or operating system.
• Breakpoints: ebreak shifts control flow directly to attached debugging infrastructure.
• Memory Synchronization: fence explicitly sequences I/O and memory accesses against other running threads or external devices.
• Instruction Synchronization: fence.i flushes instruction pipelines to ensure recent memory stores are immediately visible to the processor’s instruction fetch stream.

These precise choices of inclusion and omission dictate the overall physical and logical efficiency of the architecture.

Architectural Trade-offs and Metrics

The cumulative structural decisions of the RV32I base integer ISA specifically target seven core architectural metrics.

• Cost & Simplicity: Omission of legacy artifacts like condition codes, complex addressing modes, integer multiply/divide, and delayed branches shrinks die area and hardware decode complexity.
• Performance: Unifying instruction lengths to 32 bits, fixing register specifier locations, and utilizing 3-operand instructions streamlines superscalar and out-of-order execution scaling.
• Architecture Isolation: Removing pipeline-exposing mechanisms like the PC register and delayed memory loads insulates the ISA from shifting hardware implementations.
• Program Size: Maintaining 32-bit boundaries creates compact bases that tightly couple with the optional 16-bit compressed extension without expanding the opcode map or requiring multiple hardware decoders.
• Ease of Programming: 31 independent general-purpose registers, PC-relative addressing formats, and unaligned data support streamline register allocation algorithms and simplify linkers.