00 Index

The RISC-V Reader: An Open Architecture Atlas

Book

• 01 Why RISC-V.pdf
• 02 RV32I - RISC-V Base Integer ISA.pdf
• 03 RISC-V Assembly Language.pdf
• 04 RV32M - Multiply and Divide.pdf
• 05 RV32FD - Single-Double Floating Point.pdf
• 06 RV32A - Atomic.pdf
• 07 RV32C - Compressed Instructions.pdf
• 08 RV32V - Vector.pdf
• 09 RV64 - 64-bit Address Instructions.pdf
• 10 RV32-64 Privileged Architecture.pdf
• 11 Future RISC-V Optional Extensions.pdf
• 12 Appendix A - RISC-V Instruction Listings.pdf

Table of contents

• 1. Why RISC-V? (printed pp. 1-13; PDF pp. 22-34)
• 2. RV32I: RISC-V Base Integer ISA (printed pp. 14-31; PDF pp. 35-52)
• 3. RISC-V Assembly Language (printed pp. 32-43; PDF pp. 53-64)
• 4. RV32M: Multiply and Divide (printed pp. 44-47; PDF pp. 65-68)
• 5. RV32FD: Single/Double Floating Point (printed pp. 48-59; PDF pp. 69-80)
• 6. RV32A: Atomic (printed pp. 60-63; PDF pp. 81-84)
• 7. RV32C: Compressed Instructions (printed pp. 64-71; PDF pp. 85-92)
• 8. RV32V: Vector (printed pp. 72-85; PDF pp. 93-106)
• 9. RV64: 64-bit Address Instructions (printed pp. 86-99; PDF pp. 107-120)
• 10. RV32/64 Privileged Architecture (printed pp. 100-115; PDF pp. 121-136)
• 11. Future RISC-V Optional Extensions (printed pp. 116-117; PDF pp. 137-138)
• A. RISC-V Instruction Listings (printed pp. 118-165; PDF pp. 139-186)

Agent: GPT-5 Codex, coding agent, 2026-05-01.