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07 Dynamic Scheduling

Overcoming Data Hazards with Dynamic Scheduling

Dynamic scheduling allows processors to execute instructions out of program order as soon as their required data dependences are resolved. This approach decouples instruction execution from the strict sequence compiled into the binary, hiding pipeline stalls caused by cache misses or high-latency operations. The mechanism heavily relies on and integrates with branch prediction, speculative execution, and register renaming to maximize instruction-level parallelism.

To execute out of order while preserving correct program semantics, specific hardware structures must track dependencies and execution state.

Hardware Structures

  • Reorder Buffer (ROB)
    • A first-in, first-out (FIFO) circular buffer managed via head and tail pointers that dictates the permanent architectural state updates.
    • Maintains functional equivalency with an in-order processor by allowing speculation recovery and guaranteeing precise exceptions.
    • Each entry tracks a single instruction using specific fields: Ready (execution completed), DestV (register output produced), Dst AReg (target architectural register), Dst PReg (target physical register), PC, and Exception/Misprediction Info.
  • Instruction Scheduler
    • Tracks operand availability (instruction wakeup) and selects ready instructions for functional unit (FU) execution (instruction dispatch).
    • Each entry tracks the dependencies of a pending instruction using the following fields: Busy, Opcode, Dst Reg, ROB entry, $V_j$ / $V_k$ (flags indicating if input registers are needed), $Reg_j$ / $Reg_k$ (physical register indices for inputs), $R_j$ / $R_k$ (flags indicating if input values are ready), and Ready (true when all valid inputs are ready).
    • Relies on broadcast buses from FUs to receive completion notifications; entry comparators match broadcasted physical register indices against $Reg_j$ and $Reg_k$ to update the $R_j$ and $R_k$ flags.

These structures orchestrate the instruction lifecycle through four distinct pipeline stages.

Four Stages of Dynamic Execution

  • Issue (In-order)
    • An instruction allocates an entry in the ROB and an entry in the instruction scheduler (or the load/store queue for memory operations).
    • If the ROB, scheduler, or load/store queue is full, the processor front-end stalls until resources free up.
  • Dispatch (Out-of-order)
    • The scheduler evaluates the Ready flags of all entries and selects a subset of instructions to send to available FUs each clock cycle.
    • Selection logic prioritizes older instructions to ensure the in-order commit process is not bottlenecked.
    • Processors frequently implement a dispatch width wider than the issue and commit widths to rapidly process bursts of ready instructions after a long-latency data hazard (e.g., a cache miss) is resolved.
  • Completion (Out-of-order)
    • The FU reads input data from the Unified Register File (URF), computes the result, and writes the value to the destination physical register.
    • The FU broadcasts a completion notification to the ROB (passing any exception or misprediction data) and the instruction scheduler.
    • The scheduler performs wakeup by comparing the broadcasted destination register to pending $Reg_j$ and $Reg_k$ fields, marking dependent instructions as Ready.
  • Commit or Recovery (In-order)
    • Commit: An instruction retires when it reaches the head of the ROB, has completed execution without exceptions, and is definitively non-speculative. The architectural register map is updated, store buffers are authorized to write to memory, and the ROB entry is freed.
    • Recovery: If the instruction at the head of the ROB contains an exception or misprediction, the ROB and pipeline are flushed, physical registers allocated by flushed instructions are released, and execution restarts at the correct PC.

The strict in-order commit process natively supports robust handling of exceptions and control flow mispredictions.

Speculation Recovery and Precise Exceptions

  • Precise Exceptions: Because architectural state updates are deferred until an instruction commits, exceptions are precise. If an instruction generates a floating-point exception or page fault, the error is recorded in the ROB. The exception is only triggered when the instruction reaches the head of the ROB, guaranteeing all preceding instructions have completed and all subsequent instructions are cleanly aborted.
  • Branch Misprediction Recovery:
    • Standard recovery waits for the mispredicted branch to reach the head of the ROB, flushes all subsequent instructions, and restores the register renaming map from the architectural map.
    • Early Recovery Optimization: High-performance processors take a checkpoint of the register renaming map when a branch issues. When a misprediction is detected, hardware immediately clears the ROB entries of younger instructions and restores the renaming map from the checkpoint, bypassing the wait for the branch to reach the ROB head. The number of pending branches is constrained by the available checkpointing hardware.

While the basic dynamic execution loop effectively mitigates data hazards, further refinements to the scheduler architecture dictate ultimate performance and clock frequency limits.

Implementation Details: Wakeup, Forwarding, and Schedulers

  • Wakeup and Scheduling Latency
    • Standard dynamic scheduling requires sequential clock cycles for wakeup, scheduling, and URF reads, inserting multi-cycle gaps between back-to-back dependent instructions.
    • Early Notification: For fixed-latency operations, FUs send completion notifications early in the execution cycle, allowing wakeup and scheduling to overlap with the final stages of execution.
    • Data Forwarding: Dispatch logic reads available physical registers directly into the scheduler, and dedicated forwarding paths pass results instantly between FUs. This bypasses the latency of writing to and reading from the URF, though it introduces a trade-off with processor clock cycle time due to added routing complexity.
  • Centralized vs. Distributed Schedulers
    • Centralized Scheduler (Unified Window): Routes instructions to any available FU, maximizing hardware utilization. However, scaling beyond 100 entries causes clock frequency bottlenecks due to the complexity of scanning all entries for wakeup and physically compacting entries to maintain age-based ordering.
    • Distributed Schedulers (Reservation Stations): Allocates small queues (4–10 entries) to specific FUs. This drastically simplifies wakeup logic and age-based compaction, making it faster to select the oldest ready instruction. Its primary drawback is load imbalance: uneven instruction mixes can fill one reservation station while others remain empty, stalling the entire issue stage.
    • Hybrid Design: Partitions schedulers by instruction class (e.g., integer vs. floating-point) but allows any scheduler in a class to dispatch to any matching FU. This prevents the underutilization seen in strict reservation stations while avoiding the massive scale of a centralized window. To avoid the clock frequency penalties of physical compaction, these schedulers utilize an age matrix to maintain execution priority dynamically.

By managing data hazards through dynamic scheduling, the processor optimizes instruction throughput, laying the foundation for handling more complex memory-based dependencies.