MMIX

\chapter{MMIX} \begin{enumerate} \item {\bfseries Structures:} \begin{enumerate} \item MMIX Computer \item The Main \item LOC \item GREG \item Instructions Labels \item Argc and Argv; $0,$1 \item Trap 0,Halt,0 \end{enumerate} \item {\bfseries First Stage:} \begin{enumerate} \item Pseudo Settings $[SET $ X, Y Z : u ($ X) \leftarrow Y Z; 0 \leq Y Z \leq 2^{16} - 1]$ \item Additions $[A DD $ X, $ Y, $ Z [Z] : s ($ X) \leftarrow s ($ Y) + s ($ Z)]$ $[A DD U $ X, $ Y, $ Z : u ($ X) \leftarrow (u ($ Y) + u ($ Z)) m o d 2^{64}]$ \item Subtractions $[S U B $ X, $ Y, $ Z [Z] : s ($ X) \leftarrow s ($ Y) - s ($ Z)]$ $[S U B U $ X, $ Y, $ Z : u ($ X) \leftarrow (u ($ Y) + u ($ Z)) m o d 2^{64}]$ \item Multiplications $[M UL $ X, $ Y, $ Z [Z] : s ($ X) \leftarrow s ($ Y) \times s ($ Z)]$ $[M ULU $ X, $ Y, $ Z : u (rH $ X) \leftarrow (u ($ Y) \times u ($ Z)]$ \item Divisions $[D I V $ X, $ Y, $ Z : $ X \leftarrow ⌊ $ Y / $ Z ⌋ [0]; r R \leftarrow $ Y m o d $ Z [$ Y]]$ $[D I V U $ X, $ Y, $ Z : $ X \leftarrow ⌊ rD $ Y / $ Z ⌋ [rD], r R \leftarrow rD $ Y m o d $ Z [$ Y]]$ \item Overflows $[r A = #40, r A = #80]$ \item Negations $[NEG $ X, Y *, $ Z [Z] : s ($ X) \leftarrow Y * - s ($ Z)]$ $[NEG U $ X, Y, $ Z : u ($ X) \leftarrow (Y - u ($ Z)) m o d 2^{64}]$ \item Comparisons $[CMP $ X, $ Y, $ Z [Z] : s ($ X) \leftarrow - 1, 0, 1 : s ($ Y) le,eq,ge s ($ Z)]$ $[CMP U $ X, $ Y, $ Z : s ($ X) \leftarrow - 1, 0, 1 : u ($ Y) le,eq,ge u ($ Z)]$ \item Taking From Specials $[P U T X, $ Z [Z] : u (g [X]) \leftarrow u ($ Z); GET $ X, Z : u ($ X) \leftarrow u (g [Z])]$ \end{enumerate} \item {\bfseries Memory Communication} \begin{enumerate} \item Assembly Puts $[L ab e l OCT A, TETR A, WY D E, B Y TE ∣ EXP s, s ∣]$ \item Reading From Memory $[L D B ∣ U, L B W ∣ U, L D T ∣ U, L D O ∣ U $ X, $ Y, $ Z [Z]; L ab e l (ab s) : s ($ X) \leftarrow s (M_{1, 2, 4, 8} [A])]$ $[A = (u ($ Y) + u ($ Z)) m o d 2^{64}]$ \item Saving Back To The Memory $[STB ∣ U, ST W ∣ U, STT ∣ U, STO ∣ U $ X, $ Y, $ Z [Z]; L ab e l (ab s) : s (M_{1, 2, 4, 8} [A]) \leftarrow s ($ X)]$ $[r A = #40]$ \item One weird piece $[STCO X, $ Y, $ Z [Z] : u (M_{8} ($ Y + $ Z)) \leftarrow X one byte as unsigned octa]$ \item Increase Readability $[N am e I S REGS ∣ CONSTS]$ \end{enumerate} \item {\bfseries Inputs, Outputs} \begin{enumerate} \item Pseudo Loading $[L D A, $ X, L ab e l : u ($ X) \leftarrow L ab e l (re l)]$ \item I/Os $[TR A P 0, Fp u t s, St d O u t; B u ff er @ ($255) : 0; $255 \leftarrow N o O f P r in t s]$ $[TR A P 0, F g e t s, St d I n; A r g @ ($255) : #10; $255 \leftarrow N o O f I n p u t s]$ $[Buffer BYTE 0; LOC Buffer+80; Arg OCTA Buffer; OCTA 80; .. LDA $255, Arg]$ \end{enumerate} \item {\bfseries Jumping Around} \begin{enumerate} \item Relative Jumps $[J MP X Y Z, L ab e l s (re l) : @ \leftarrow R A; R A = @ \pm 4 * X Y Z]$ \item Getting Forward Addresses $[GET A $ X, Y Z u ($ X) \leftarrow R A]$ \item Absolute Jumps $[GO $ X, $ Y, $ Z [Z]; L ab e l s : u ($ X) \leftarrow @ + 4, @ \leftarrow A]$ \item Conditional Statements $[P ∣ BZ, NZ, N, NN, P, NP, O D, E V $ X, Y Z; L ab e l s (re l) : o n ?, @ \leftarrow R A]$ \item Local Labels $[decimalH; ForwardRef:decimalB, BackwardRef:decimalF]$ \item Conditional Assignements $[CS xx, ZS xx $ X, $ Y, $ Z [Z] : o n ?, s ($ X) \leftarrow s ($ Z)]$ \end{enumerate} \item {\bfseries SubRoutines} \begin{enumerate} \item Foreground $[rL = no(LocalRegs) = nexcount(NextRegs); rG[32:255] = count(GlobalRes)]$ \item Prefixing $[PREF I X N am e :; :\to N am e :]$ \item Pushing The Stack $[P U S H J, P U S H GO $ X, Y Z; L ab e l (re l, ab s)]$ $[S [] : $0, $ (X - 1); $ X = n o (H i dd s); r L s = $ X + 1, $ X + 2 : $0, $1; r J \leftarrow @ + 4; @ \leftarrow A]$ $[X \geq r L ? r L + + : $ X \in r L s, X \geq r G ? X = r L]$ \item Poping The Stack $[POP X, Y Z : @ \leftarrow R A (r J), S [τ] = $ (X - 1), $ (τ + 1) = $0, $ (τ + 2) = $1]$ $[X > r L ? : X = r L + 1]$ \end{enumerate} \item {\bfseries Data Structures} \begin{enumerate} \item Gating $[A N D, OR, XOR, N A N D, NOR, NXOR, A N D N, ORN $ X, $ Y, $ Z [Z]]$ Eg: $[A \to a : OR $1, $1, 32; a \to A : A N D $1, $1, # D F]$ $[A \leftrightarrow B : XOR $ X, $ Y, $ X; XOR $ Y, $ X, $ Y; XOR $ X, $ Y, $ X]$ \item BitShifting $[S L ∣ U $ X, $ Y, $ Z [Z] : s ($ X) \leftarrow s ($ Y) \times 2^{s ($ Z)}; r A = #40]$ $[SR ∣ U $ X, $ Y, $ Z [Z] : s ($ X) \leftarrow ⌊ s ($ Y) / 2^{s ($ Z)} ⌋]$ \item 2Bytes Setting $[SET H, M H, M L, L $ X, Y Z : u ($ X) \leftarrow Y Z \times 2^{48, 32, 16, 0}]$ $[I NC H, M H, M L, L $ X, Y Z : u ($ X) \leftarrow (u ($ X) + Y Z \times 2^{48, 32, 16, 0}) m o d 2^{64}]$ $[A N D N, OR H, M H, M L, L $ X, Y Z : $ X \leftarrow $ X * Y Z \times 2^{48, 32, 16, 0}]$ \item Miscallenous $[S A DD $ X, $ Y, $ Z : s ($ X) \leftarrow s (\sum (v ($ Y) & \sim ($ Z)))]$ $in how many places Y has 1 and Z has 0$ $[M U X $ X, $ Y, $ Z : v ($ X) \leftarrow (v ($ Y) & v (r M)) ∣∣ (v ($ Z) & v (r M))]$ $[The bits are taken from Y, when the bit in rM is 1 and from Z if in rM is 0.]$ \item Addressing $[differences in relative and absolute addressing and the use of GREG]$ $can also set addresses using SET family$ $[L D A, 2 A DD U, 4 A DD U, 8 A DD U $ X, $ Y, $ Z [Z] : u ($ X) \leftarrow u ($ Y) * s + $ Z]$ \end{enumerate} \item Floating Numbers \begin{enumerate} \item Floating Introduction $[S : 1 b, E : 11 b, F : 52 b; O, U, Z, I]$ $[E = 0, F = 0 : \pm 0.0]$ $[E = 0, F \neq = 0 : \pm 2^{- 1074} F]$ $[0 < E < 2047 : \pm 2^{E - 1023} (1 + \frac{F}{2 ^{52}}); (- 1)^{S} (F) (2^{- (B - 1)}) \infty]$ $[E = 2047, F = 0 : \pm \infty]$ $[E = 2047, F \neq = 0 : \pm N a N (\frac{F}{2 ^{52}})]$ \item Conversions $[F L OT ∣ U $ X, $ Z [Z] : f ($ X) \leftarrow s ($ Z); f ($ X) \leftarrow u ($ Z)]$ $[F I X ∣ U $ X, $ Z : s ($ X) \leftarrow in t f ($ Z); u ($ X) \leftarrow in t f ($ Z) m o d 2^{64}]$ \item Arithmetic $[F A DD, FS U B, FM UL, F D I V, FREM $ X, $ Y, $ Z]$ $[f ($ X) \leftarrow f ($ Y) + f ($ Z); f ($ X) - f ($ Y); f ($ Y) * f ($ Z); f ($ Y) / f ($ Z); f ($ Y) m o d f ($ Z)]$ $[F I NT, FSQRT $ X, $ Z : f ($ X) \leftarrow in t f ($ Z); f ($ X)^{\frac{1}{2}}]$ \item Comparisons $[see screenshots somewhat complicated]$ \item Short Float Conversions $also same$ \item Loading and storing of short floats $bla bla come back later$ \end{enumerate} \item Fields $address of ith element = address of field + address of + i*size of element$ \begin{enumerate} \item Address Calculation nice $[s [2, 4, 8, 16] A DD U $ X, $ Y, $ Z [Z] : u ($ X) \leftarrow u ($ Y) \times s + u ($ Z)]$ \end{enumerate} \item Graphics $[L DH T $ X, $ Y, $ Z [Z] : u ($ X) \leftarrow u (M_{4} [$ Y + $ Z]) \times 2^{32}]]$ $[ST H T $ X, $ Y, $ Z [Z] : u (M_{4} ($ Y + $ Z)) \leftarrow ⌊ u ($ X) / 2^{32} ⌋]$ \item Bitmap $[MOR, MXOR $ X, $ Y, $ Z : matrix multiplication but with +,or and +,xor]$ \item Some more $[B D I F, W D I F, T D I F, O D I F $ X, $ Y, $ Z : x \leftarrow ma x (0, y - z)]$ \end{enumerate} Taking From Special Registers

[The following registers cannot be written to: rC, rL, rN, rD, rS, rI, rT, rTT, rK, rQ, rU and rV. No value can be written to rG that is smaller than 32 (or lower than the value currently contained in rL) or greater than 255. No value can be written to rA that is greater than \#3FFFF]

 Expressions
[considered as octabytes]
\begin{figure}[H]
\centering
\includegraphics[width=\textwidth]{expressions.png}
[\$ allowed only as regi+pure, pure+reg, reg-pure, reg-reg while weak binary cant be on reg,reg gives reg no while the last just give pure value as \$ get canceled]

\end{figure} \section{Control Unit} [actually the commands are carried out in many different steps controlled by control unit, the control unit has command register that has the address of the next command. It has a PC register that store the memory address of the next instruction to be carried out and instruction register that includes the command in encoded form]

$F e t c h F, Deco d eD, E x ec u e X, M e m ory A ccess M, W r i t e - B a c kW$ $idea of stalling taking 3u due to bad guess$ \begin{enumerate} \item Good guys sympathize $[S WY M X, Y, Z : gives cpu a break]$ \item Interreuptions $synchronous; happens again in the same place; and asynchronous handling; outside of the program; also deliberate$

$$[program,timer,i/o,hardware failure: control jumps from the program to interrupt handler of OS (trap),or of user(trip)]$$

\end{enumerate} \chapter{Information Structures} \section{Prerequisites} \begin{enumerate} \item Terminology:\par [The information in a list consists of a set of nodes, each of which consists of one or more consecutive words of the computer memory, divided into named parts called fields, meanwhile the memory address of a node, taken relative to a base location is called link to that node] \item Notations:\par \begin{center} \begin{itemize} \item {[Referring to fields within a node:]} $[FIELD_NAME(LINK_TO_THE_NODE)]$ \item {[Denoting a whole node:]} $[VAR_NAME \leftarrow NODE(LINK_TO_THE_NODE)]$ \item {[Converting between addresses and values stored of a node:]} $[CONTENTS(LINK_TO_THE_A_OCTA_NODE); LOC(NAME_OF_THE_A_OCTA_VAR)]$ \end{itemize} \end{center} \end{enumerate} \section{Linear Lists} \begin{enumerate} \item Definition:\par [A linear list is a sequence of $n \geq 0$ nodes] $[X [1], X [2], \dots X [n]]$ [whose essential properties involve only the relative positions between items as they appear in a line that] \begin{itemize} \item {[if $n > 0$ , $X [1]$ is the first node and $X [n]$ is the last]} \item {[if $1 < k < n$ , $X [k]$ is preceded by $X [k - 1]$ and followed by $X [k + 1]$ ]} \end{itemize} \item Desired Operations:\par \begin{enumerate} \item {[Gain access to the kth node of the list to examine and/or to change the contents of its fields]} \item {[Insert a new node just before or after the kth node]} \item {[Delete the kth node]} \item {[Combine two or more linear lists into a single list]} \item {[Split a linear list into two or more lists]} \item {[Make a copy of a linear list]} \item {[Determine the number of nodes in a list]} \item {[Sort the nodes of the list into ascending order based on certain fields of the nodes]} \item {[Search the list for the occurrence of a node with a particular value in some field]} \end{enumerate} \item Special Names:\par [Linear lists in which insertions, deletions, and accesses to values occur almost always at the first or the last node are very frequently encountered] \begin{itemize} \item {[A stack is a linear list for which all insertions and deletions (and usually all accesses) are made at one end of the list (FIFO)]} \item {[A queue is a linear list for which all insertions are made at one end of the list; all deletions (and usually all accesses) are made at the other end (LIFO)]} \item {[A deque (“double-ended queue”) is a linear list for which all insertions and deletions (and usually all accesses) are made at the ends of the list]} $***Train Analogy Goes Here***$ \end{itemize} \item Stacks’ Applications: \begin{itemize} \item {[problem solving approach]} \item {[entering and exiting the subroutines]} \item {[processing of languages with nested structures]} \item {[recursive algorithms]} \end{itemize} \end{enumerate} \subsection{Sequential Allocation} \begin{enumerate} \item Principles $[LOC (X [j + 1]) = LOC (X [j]) + c [offset], LOC (X [j]) = L_{0} [base] + c j]$ \item Stacks [First Draft: Pointer T]: $[Empty Stack: T = 0]$ $[X \Leftarrow Y : T \leftarrow T + 1; X [T] \leftarrow Y]$ $[Y \Leftarrow X : Y \leftarrow X[T]; T \leftarrow T - 1]$ \item Queues [First Draft: Pointer F and R]: $[Empty Queue: F = R = 0]$ $[X \Leftarrow Y : R \leftarrow R + 1; X [R] \leftarrow Y]$ $[Y \Leftarrow X : F \leftarrow F + 1; Y \leftarrow X [F]; if F = R then F \leftarrow R \leftarrow 0]$ \item Queues [Second Draft: X[1] follows X[M]] $[X \Leftarrow Y : if R = M then R \leftarrow 1; else: R \leftarrow R + 1; X[R] \leftarrow Y;]$ $[Y \Leftarrow X : if F = M then F \leftarrow 1; else: F \leftarrow F + 1; Y \leftarrow X[F];]$ \item Stacks [Second Draft: Memory Restrictions]

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MMIX