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09 RV64

RV64: 64-bit Address Instructions

Architectural Expansion

RV64 transitions the 32-bit RISC-V architecture to a 64-bit address space by expanding all registers, including the program counter (PC), to 64 bits.

  • The default operational data size becomes 64 bits.
  • The transition requires only a few additional word, doubleword, or long versions of existing 32-bit instructions rather than a complete instruction set overhaul.
  • Valid 32-bit words remain fully supported as data types, alongside bytes and halfwords.

Expanding the baseline register width requires specific instructions to handle narrower 32-bit operations correctly.

RV64I Base Integer Instruction Additions

RV64I introduces specific instructions to manage 32-bit data within 64-bit registers, ensuring proper truncation and extension.

  • 32-bit Word Arithmetic:
    • New word-sized addition and subtraction instructions (addw, addiw, subw) compute values, truncate the results to 32 bits, and write the sign-extended results into the 64-bit destination register.
  • 32-bit Word Shifts:
    • New shift instructions (sllw, slliw, srlw, srliw, sraw, sraiw) generate explicit 32-bit shift results.
  • 64-bit Data Transfers:
    • Doubleword memory operations utilize ld (load doubleword) and sd (store doubleword) to transfer 8 bytes at a time.
  • Unsigned Word Loading:
    • The lwu (load word unsigned) instruction loads a 32-bit word and zero-extends it to 64 bits.
    • The baseline lw instruction inherently sign-extends the 32-bit word to 64 bits in RV64I.

The strategy of appending specific size variations to base instructions extends beyond integer logic into math, atomic, and floating-point extensions.

Extension Adaptations (RV64M, RV64A, RV64F/D, RV64C)

Standard extensions incorporate doubleword or long variations to manipulate 64-bit values natively.

  • Multiply and Divide (RV64M):
    • Incorporates 32-bit word versions of multiplication, division, and remainder operations (mulw, divw, divuw, remw, remuw).
  • Atomic Instructions (RV64A):
    • Adds doubleword variants for all 11 atomic memory operations (e.g., amoadd.d, lr.d, sc.d) to support 64-bit synchronization.
  • Floating-Point (RV64F, RV64D):
    • Introduces integer doublewords, referred to as longs to prevent confusion with double-precision floating-point data, for conversion instructions (e.g., fcvt.l.s, fcvt.lu.d).
    • RV64D adds fmv.x.d and fmv.d.x to enable direct 64-bit data movement between integer and floating-point registers.
  • Compressed Instructions (RV64C):
    • Diverges from the strict superset relationship seen between RV64I and RV32I.
    • Eliminates the compressed jump and link (c.jal) and all word-sized load/store instructions (c.lw, c.sw, c.flw, etc.).
    • Replaces dropped instructions with 64-bit optimized operations: c.addw, c.addiw, c.subw, c.ld, c.sd, c.ldsp, and c.sdsp.

Supporting this 64-bit architectural model requires corresponding Application Binary Interfaces to govern data types and facilitate compact compiled binaries.

Application Binary Interfaces and Program Size

Software compatibility and memory footprint efficiency are maintained through defined ABIs and highly optimized code density.

  • RV64 ABIs:
    • Utilizes lp64, lp64f, and lp64d standards.
    • C language long and pointer data types span 64 bits, while int remains 32 bits.
    • Suffixes f and d specify whether single- or double-precision floating-point arguments are passed in floating-point registers.
  • Code Density:
    • RV64GC code size is practically identical to RV32GC, measuring only 1% larger overall.
    • The resulting binaries are 23% smaller than ARM-64 code and 34% smaller than x86-64 code.
    • This compact size directly reduces hardware costs or yields higher performance by lowering instruction cache miss rates.

The highly compact memory footprint of RV64 stems from foundational design choices that contrast sharply with the evolution of other major 64-bit instruction sets.

Comparisons to Alternative 64-bit ISAs

Historically, running out of address bits forced architectures into complex transitions; RV64 avoids common pitfalls by developing 32-bit and 64-bit ISAs concurrently.

  • x86-64:
    • Transitioned from x86-32 by doubling integer and SIMD registers to 16 and adding PC-relative data addressing.
    • Required prefix bytes to fit new operations and expanded registers into the existing opcode space, which fundamentally increased the average instruction length and expanded total code size.
  • ARM-64:
    • Invented a completely new, maximalist ISA with over 1000 instructions rather than directly extending ARM-32.
    • Increased registers from 15 to 31, removed the PC from the general register set, and hardwired a zero register.
    • Abandoned the 16-bit Thumb-2 compressed format, forcing all instructions to be 32 bits, making ARM-64 code 25% larger than ARM Thumb-2 code.
  • The RISC-V Advantage:
    • Simultaneous engineering of RV32 and RV64 prevented 64-bit instructions from being forced into a cramped 32-bit opcode space.
    • RV64I retains virtually all RV32I instructions, significantly simplifying the transition for compiler writers and programmers.
    • Ample opcode space allows for powerful extensions like RV64C, sustaining RISC-V’s significant lead in code density.