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09 RV64

RV64

RV64 widens all registers (including the PC) to 64 bits and adds a minimal set of word/doubleword variants to the RV32 base. The architecture structure is preserved — no overhaul required.

RV64I additions

  • Word arithmetic: addw, addiw, subw — compute in 32 bits, sign-extend result to 64 bits.
  • Word shifts: sllw, slliw, srlw, srliw, sraw, sraiw — explicit 32-bit shift results.
  • Doubleword memory: ld / sd — transfer 8 bytes at a time.
  • Unsigned word load: lwu zero-extends a 32-bit load to 64 bits; the existing lw sign-extends.

Extension adaptations

  • RV64M: adds word multiply/divide/remainder variants — mulw, divw, divuw, remw, remuw.
  • RV64A: adds doubleword variants for all 11 atomics — amoadd.d, lr.d, sc.d, etc.
  • RV64F/D: adds long (64-bit integer) conversion instructions — fcvt.l.s, fcvt.lu.d, etc. RV64D also adds fmv.x.d and fmv.d.x for direct 64-bit moves between integer and FP registers.
  • RV64C: drops c.jal and all word-sized compressed loads/stores; replaces them with 64-bit variants — c.ld, c.sd, c.addw, c.addiw, c.subw, c.ldsp, c.sdsp.

ABIs

  • lp64: long and pointers are 64 bits; int stays 32 bits; FP args use integer registers.
  • lp64f / lp64d: single- or double-precision FP arguments pass through FP registers.

Code density

RV64GC is only 1% larger than RV32GC. Compared to other 64-bit ISAs:

  • 23% smaller than ARM-64 (which dropped Thumb-2 compressed format entirely).
  • 34% smaller than x86-64 (which burns bytes on legacy prefix encoding).

Comparison to other 64-bit ISAs

  • x86-64: extended x86-32 by doubling registers and adding PC-relative data addressing, but required prefix bytes to fit new operations into an already-full opcode space — inflating average instruction length.
  • ARM-64: invented a brand-new 1000+ instruction ISA rather than extending ARM-32. Gained 31 registers and a hardwired zero, but dropped Thumb-2, making ARM-64 code 25% larger than ARM Thumb-2.
  • RISC-V: RV32 and RV64 were engineered simultaneously, so 64-bit instructions were never forced into a cramped 32-bit opcode space. RV64I retains virtually all RV32I instructions, keeping the compiler transition simple.