Instrumentation

Matching with peripherals:

Parallel interfacing: >8255A is a widely used, programmable, parallel I/O device which can be programmed to transfer data under various conditions, from simple I/O to interrupt I/O >has 24 I/O pins that can be grouped primarily in two 8-bit paralle ports: A and B, with the remaining eight bits as port C which can be used as individual bits or be grouped in two 4-bit prots: Cupper and Clower. >the functions of thse ports can be classified accordint to two modes: BSRT mode and the IO mode; the bsr is used to set or reset the bits in port C, while IO is further divided into three modes, mode 0,1,2. In mode 0, all ports function as simple I/O ports. Mode 1 is a handshake mode whereby ports A and/or B use bits from port C as handshake signals. In the handshake mode, two types of IO tarnsfre can be implemented: status check and interupt. In mode 2, port A can be set up for bidirectional data transformer using handshake signals from port C, and port B can be set up either as in mode 0 or 1 >The function of these ports are defined by writing a controlw ord in the control register in the following steps: i) Determine the address of ports A,B and C and of the control register according to chip select logic and address lines A0, A1 ii) Write a control word in control register iii) Write I/O instructions to communicate with peripheral through A, B and C CONTROL WORD: D7(IO/BSR), D6,D5(A_MODE), D4(A_IO), D3(CU_IO), D2(B_MODE), D1(B_IO), D0(CU_IO) (BLOCK PIC)

BSR Mode: >control word with D7=0 is recognized as a BSR which is concerned with eight bits of port C, which can be set or reset by writing an appropriate control word in the control register. D7=0, D6,D5,D4=X, D3,D2,D1=bit of port C, D0=set/reset

Mode 0: >Features: ports A and B are used as two simple 8-bit I/O ports port C as two 4-bit ports. ports do not have handshake or interrupt capability outputs are latched, inputs are not latched

Mode 1: >handshake signals are exchange between the MPU and peripheral prior to data transfer >Features: ports A and B are used as I/O ports that uses three lines from port C each as handshake signals remaining two lines of port C are used for simple IO functions interrupt logic is supported both input and output data are latched

>CONTROL SIGNALS:
	Port B uses PC0 (INTR), PC1 (IBF), PC2 (STB') in input or PC0 (INTR), PC1 (OBF'), PC2 (ACK)
	port A uses PC3 (INTR), PC5 (IBF), PC4 (STB') in input or PC3 (INTR), PC7 (OBF'), PC6 (ACK)
	[THE internal PICS]
	<The inputs it receives are on PC2, PC4 and PC6>
	[TIMING DIAGRAMS]
		FOR INPUT (mup lai data dinxa) so gets STB' from peripheral and gets RD' from mup
		>RD' and STB' are the causes, IBF and INTR are the effects; STB' causes to go up while RD' causes to go down
		>(peripheral writes here) STB' down -> IBF up; STB' up -> INTR up; RD' down -> INTR down; RD' up -> IBF down 
		FOR OUTPUT (mup bata data linxa) so gets WR' from mup and gets ACK from peripheral
		>WR' and ACK are the causes, OBF' and INTR are the effects; WR' causes to go down and ACK causes to go up
		>(intially INTR is on to signify that it wants data)
		>WR' down -> INTR down; WR' up -> OBF' down; (peripheral reads here); ACK' down -> OBF' up; ACK' up -> INTR up
>STATUS WORD: (for polling)
	SAME AS CONTROL SIGNALS, EXCEPT THE INPUT SIGNALS (STB', ACK) REPLACE THE ENABLE FLIPFLOP
	

Mode 2: >primarily in applications such as data transfer between two computers or floppy disk controller interface. Port A can be configured as bidirectional port and port B either in mode 0 or mode 1. Port A uses five signals from port C as handshakes and remaining 3 can be used as simple I/O or handshake for port B

INTERFACING DAC AND ADC: >A DA converter circuit rquires a resister network with appropriate wieghitng (each twice than before), switches and reference source >It includes DA converter, the succesive approximation register and the comprator. Involves comparing the output of the DA converter V0 with the analog input signal Vin i) First 1401(8-bit) using a decoder, latch, and opamp (like an output device, LED) industry standard compatible with cmos and ttl logic which has eight input lines, requires two power supplies, and reference current is determined by the register R14, also has a register R15 to match the input impedance of reference source ii) Second AD7255(10-bit) using a decoder and a opamp is a 10 bit DA converter which are loaded into input in two steps, lower loaded with control line LBS, remaining two with HBS then all ten bits are switched for conversion by line LDAC iii) General AD converter in status check: simple iv) AD0801 for interrupt: has two inputs VIn+ and Vin- for differential signal, for single ended positive, vin-is grounded. Requires a clk at clk in or use internal clcok cy connecting a register and capacitor

Parameters of DAC: >The number of possible output levels the DAC is designed to reproduce. This is usually stated as the number of bits it uses, which is the binary logarithm of the number of levels. For instance a 1-bit DAC is designed to reproduce 2 (21) levels while an 8-bit DAC is designed for 256 (28) levels. >Linearity, accuracy: is how much the value under measurement deviates from its true value >Monotonicity: The ability of a DAC’s analog output to move only in the direction that the digital input moves (i.e., if the input increases, the output doesn’t dip before asserting the correct output.) >Settling time: oscillates briefly around the output, time to enter the error band value; 1408 has setttling time of around 300ns

Parameters of ADC: (primarily by bandwidth (by sampling rate) and snr by resolutioni, linearity, accuracy) >An analog signal is continuous in time and it is necessary to convert this to a flow of digital values. It is therefore required to define the rate at which new digital values are sampled from the analog signal. The rate of new values is called the sampling rate or sampling frequency of the converter || Conversion time: total time to convert an analog value to digital, 100us conversion time for ad0801 >The resolution of the converter indicates the number of different, ie discrete, values it can produce over the allowed range of analog input values. For example, an ADC with a resolution of 8 bits can encode an analog input to one in 256 different levels (28 = 256). >All ADCs suffer from nonlinearity errors caused by their physical imperfections, causing their output to deviate from a linear function of their input >An ADC has several sources of errors. Quantization error and (assuming the ADC is intended to be linear) non-linearity are intrinsic to any analog-to-digital conversion.

ERRORS: DYNAMIC: essential for med- or high frequency ADC and DACs: (FIGURE) i) DAC settling time: The output of the DAC oscillates around it’s actual value before it settles down to it. The time takes for the output of the DAC to settle down to a specified error band is called it’s settling time. It’s 300ns for 1401 DAC ii) ADC conversion time: Total time to convert an analogy signal to digital, 100us for AD0801 iii) Delay time (output starts moving from its previous value)

STATIC:
i) Differential NonLinearity: (no comparison with ideal)
	difference between an actual step height (for a DAC) or step width (for an ADC) and the ideal value of 1 LSB. If step or height is exactly 1 LSB, differential nonlinearity is zero. If exteeds one, the converter becomes nonmonotonic
	(fig) 
ii) Integral Linearity: (comparison with ideal)
	is ther deviation of the values on the actual transfer function from a straight line. The st line could be a best st line ddrawn to minimize deviations or it can be line drawn between end points once gain and offset errors are nullified. For dac they are measured at each step, for adc measured at transitions from one step to the enxt
	>Endpoints linearity
	>Bestfit linearity
	>Absolute error: Analog-to-Digital Converter (ADC) absolute error (absolute accuracy) is the total uncompensated error and includes quantization error, offset error, gain error, and non-linearity.
		>Offset error: difference between nominal and actual offset points. FOr an dac it is the step value when digital input is zero wile for DC the ofset point is the midstep value when digital output is zero
		>Gain error: difference between nominal and actual gain points after offset is corrected to zero. For dac is the step value when digital input is full space. For adc is the midstep value when the digital output is full value
		
		
		
		
		
		

NEW WORLD OF ABSTRACTION: >PC is the sum of subsystems, at each boundary of subsystems and another, we find an interface, a electric system that connects the two subsystems together and enables them to exchange data >accurately it refers to a standard, a set of rules for the exchange data, in practice an interface consist of two controllers (one at each end of connection), a cable , some protocols contained in the controller; in general, controllers are inside the device >there are several buses in motherboard, two buses with different bandwidth can be connected if we place a controller between them, often called bridge; so there are not many controllers on motherboard; which are placed on a chip called chipsest >The north chipset connects CPU slot (100MHz), RAMs (around that bus higher), AGP slot(replaced by PCIe), Ethernet so CPU would contain a controller and northchip would another controller hence making an interface data rate = frequency*64/clock cycles per transfer >Sourthbrdige: BIOS ROM (BIOS has startup programs which feed on CMOS data that can be changed during the startup), PCI slots (contains SCSI, both serial and apralle): harddisk, cdrom etc replaced by ATA, Firewire (series) controller: camera), USBs (serial), ATA with RAID controller (both), supplemented by Super IO

FROM ISA TO PCIexpress: >kept for compatiblity as sound cards worked quite well with ISA and many games were programmed to exploit that kind of hardware >ISA is commonly reffered to 8-bit PC/XT or improvement 16-bit PC/AT bus. >PC/XT us ia an eight bit ISA bus used by intel 8086 sysems in IBM PC. Among its 62 pins were demultiplexed into 8-bit data, 16-bit address buses along with read/write strobes and interrupt lines. GIves eight vectorized and priortized interrupts. Also four DMAs, first for dyanmic refresh, seond to add=on cards, trhhid to flooppy controller and 3rd to hard disk controoller; clock of 4.77MHz >PC/AT is a 16 bit version which adds four additional address lines and 8 additional data, extends by adding a second shorter edge connnecter in line with eight bit XT bus onenctor, 8.33MHz DISADVANTAGES: >had only 16 data channelss, so 32 bits processors needed two words, one at a time which slowed; >not intellgient as CPU had to control it so wait until transfer is complete (waitstates) >had to handle IRQ’s and DMA’s by hand >replace dby EISA and PCI

PCI WORLD:
>peripheral component interconnect an intel product which is processor independent used in all PCs 32-bit or 64-bit today.
>33.33 Mhz with synchronous transer, at peak rate of 133MB/s
>32 bit bus width with 32- or 64-bit memory address space
>5-volt signaling
>also proides 64 bit bus width but not used outside PCI-X servers
>compatible to ISA to some extent as creates same IRQ and DMAs;
>PCI adapter cards are self configuring (plug and play)

SERIAL INTERFACING: >process of sending data one bit at a time, sequentially, over a communication channel or computer bus. in constrast to parallel communication, where several bits are sent as a whole, on a link with several parallel channels >Used for all longhaul communication and computer networks where cost of cable and synchronization difficulties make parallel impractical >Cables and ports transmitting one bit at a time include serial ATA, serial SCSI, ethernet cable, USBs >ADVANTAGES: →requires fewer interconnecting cables hence occupies less space →crosstalk is les of an issue there are fewer conductors in proximity →budgets for power use, power dissipation, cable cost, etc →ICs used are less expensive

SYNCHRONOUS: >describes a serial communication protocol in which data is sent in a continuous stream at a constant rate >requires that the clocks in the transmitting and receiving devices are synchronized-running at the same rate so receiver can sample the signal at the same time inverals used by the transmitter. >No start or stop bits are required so no block coding is required (does not add to baud rate) >Over time transmitting and receiving clocks will tend to drift apart, requiring resynchronization >Byte-oriented protocols: where synchronization was maintained by transmitting a sequence of synchronous idle characters prior to each transmission >Bit-oriented proctorls: views transmitted data as a stream of bits with no meaning so control codes are transmitted as a predefined

ASYNCHRONOUS: >a form of serial in which communicating end points interfaces are not continouosly synchronized by a common clock signal >Instead of a common syncrhonization signal, the data stream contains synchronization information in form of start and stop signals before and after each unit of transmission, respectively >In typewriters the ASCII characters were transmitted in the following frame: 1 start bit: beginning of data 7-bit ahracter: actual ascii data 1 partiy; parity 2 stop bits: end of data

ERROS: UART or Universal Asynchronous Receiver Transmitter is a serial communication device that performs parallel – to – serial data conversion at the transmitter side and serial – to – parallel data conversion at the receiver side. It makes use of buffer and shift registers along with SDU logic.

Framing error: In serial communications, a framing error is the result of reading a data frame at the wrong starting point. So data does not fit in frame that data format and baud rate defined. A framing error in an asynchronous stream usually recovers quickly, but a framing error in a synchronous stream produces gibberish at the end of the packet. Framing errors can be detected with parity bits.

Break error: when transmitter is holding the start bit at low logic for more than expected so receiver assumes that the connection to transmitter has brokern

Receiver overrun: one or more characters are received but not read from the buffer as latter received byte overwrites the older. Transmitting faster than receiving

Parity error: occurs when an odd number of bits change value. Detected by parity bit

1. Parity check:

   Parity bit is an additional bit added to the data at the transmitter before transmitting the data which corresponds to number of 1’s or 0’s in the datas

2. Checksum:

   Block code method where a checksum is created based on the data values in the data blocks to be transmitted using some algorithm and appended to thte data. Data is divided into fixed sized segments, the sender adds the segments using 1’s complement arithmetic to get the sum. Then complements the sum to get the checksum and sends it along the data frame Reeier adds the incoming segment along with checksum using 1’s complement arithmetic to get the sum and then complements it, if result is zero, reveiced frames are accepted else degraded

3. Cyclic redundancy check (CRC):

   The CRC is based on polynomial manipulations which treat each received message as a binary number. The received message is then divided by a fixed value, also known as the generator polynomial, using modulo-2 arithmetic Multiple error detection; gives the position of bit or bits which are toggled at the receiver with respect to the transmitter

SERIAL STANDARDS: >R232 is a standard for serial ransmission of data that formally defines signals connecting between a DTE (data terminal equipment) such as computer terminal and a DCE (data communication equipment equipmment) such as modem. (probably like between device and controller when they were different things) >it defines the electrical cahracteristics and timing signals, the meaning of signals, and pinout of connectors. >does not define such elements as character encoding, the framing of characters or error detection 1. Voltage levels: For data transmission lines logic one is represented as a negative voltage and signal condition is called mark (-3V to -15V) . Logic zero is signalled with a positive voltage and the signal condition is termed space (3V to 15V). Control signals have opposite polarity. MC1488 line driver converts TTL to RS-232 while MC1489 line receiver converts RS-232 to TTL 2. Connectors: Devices as DTE or DCE, male connector have DTE pin functions, and female have DCE pin functions (sharp bhako haru computer ma jodinxa). Standard recommends 25-pin connectors called DB25 while most devices only implement a few of twently singals specified in standard so most PC replaes by DE-9 3. Cables: does ont define maximum cable length but instead defines maximum capacitance that a compliant driver must tolerate 4. Pinouts: (named from the standpoint of DTE) (PIC IN FOLDER) We will be needing Request to send and Ready to receive/send → DTE sends RTS (request), RTR (receive ready), DTR (general) → DCE has (none), CTS (receive ready), DSR (genearl); also DCD, RI → DTE sends Transmitted data and receives received data, common ground >Null model is communicatoin method to directly connect two DTEs where TxD ←> RxD RTS ←> DCD DTR ←> DSR >The DTE asserts RTS to indicate a desire to transmit to the DCE, and in response the DCE asserts CTS to grant permission, once synchronization with the DCE at the far end is achieved >RS-423 uses same signalling as RS-232 which offers greater cable length as long a 1200 metres >RS-422 (same as 423 but different wiring arrangements) uses differential signalling and provides longer cable length, higher speed, immune to noise, key advantages include differential receiver, differential driver and data rates as high as 10 megabits per sceonds. (Does not use common ground so if devices are far enough apart the ground will degrade them and communications will fail)

UNIVERSAL SERIAL BUS: >is an industry standard that specifies cables, connectors and protocols for connection, communication and power supply between computers and peripherals. Designed with motivations fo developing the USB was to simply the interconnections by reducing number of cables that are coonencted to computer and by using same type of connction for various categories of perihperas. FEAUTURES: >Automatic onfiguration: the controller manages driver software and allocates bandwidth to each USB device attached to bus. when one is added or removed, automatically loads or unloads driver for that device >Hot swapping: perihperals can be connected to and disconnected from the bus at any time without shutting down the computer or taking any action to inform OS >INterrupts sharing: A usb host controller occupies one interrupts which is shared among all devices attached to the bus >Bandwidth sharing: Bandwidth is shared among devices attached to the bus. Properly designed peripheal use bandwidh dynamically, by releasing bandwidth they are not using so can be used by other >Embedded power connections: in addition to providng data coonection, USB provides electiracl pwoer to perihpaeral elimiating tangle of power cables requied by tradiional peripheral. >Expandability: Upto 127 different peripheral devices may theoritically be connected to a single bus at one time

BUS TOPOLOGY:
>The devices on the USB are physcally connected to the host computer using a start topology on several tiers. There are two categories of USB devices: hubs and functions. (TREE PIC)
>A hub provides additional attachment points for other USB devices (these attachment points are calle dprots). The host computer comtains a root hub, whcih provies one or more attachment points. In addition, the root hub contains the USB bus controller.
>A function is a USB device that is able to send or receive data or control information over the bus. A function is usually implemented as a separate peripheral connected to a port of a hub. HOwever a single physical device may contain multple functions like a keyboard and a tracking device may be combined into a single physical device where individual functions are connected to a internal hub which is then connected to the USB. (so my guess is there is no literal distinction between hub and a device)
>With the first USB versions, there were two specifications for the bus host controllers: first UHCI by intel for simple circuitry and complex hardware and OHCIalloweed simplifying hardware by complicating software. With 2.0, EHCI was by intel and xHCI by others. 
FUNCTIONS OF HOST:
	>Monitoring the insertion and removal of usb devices
	>Power managing individual devices on its ports
	>Initiates the communiation by polling the devices by using a polling interval that is determined by the device
	>And all others like bandwidth, interrupts
	>Standard compiance
FUNCTIONS OF HUB:
	>Allows multile usb deivces attach to a single port
	>Manage upstream and downstream flow of data
FUNCTIONS OF DEVICE:
	>Transmit or receive data or control information over the bus and provides function
	>manage power

USB 1.x: >maximum transfer rate specified by thse is 12 Mbits/seconds, enough for speakers, while for slow as as keyboards low speed channel 1.5Mbits/s has been provided >did not allow for extension cables due to timing and power limitations >1.0 did not catch market

USB 2.0: >also known as hispeed allows transfer rate with a factor of 40 giving 480Mbits/s. Uses same cables and connectors but now supports other high speed devices >USB 2.0 peripherals with higher transfer rates are connected to USB 2.0 hub. A USB 2.0 can also supply data with the rates corresponding to the USB2.0 and USB1.1 peripherals at their own rates (12mbits or 1.5 mbits)

>The USB "On-The'GO" OTG specifiaiotns have been developed as a supplement to the usb 2.0 speficiatons with the main aim to allow direct connection between mobile devies without using acommputer. The standard USB uses a master,slave architeure where the host computer has master role, and a peripheral has the slave roe. Only the host computer can initiate data transfers over the bus. Peripherals can only respond to thransfer requests initiated by the host computer. With OTG a peripheral ca have either the master or the slave role. The master and slave roles can be exchanged dynamically during the operation with a protocl called host negotiation protocl. Thus any peripheral compatible with USB OTG specifications can initate data transfer over the bust. The condition is that the two devices communicate directlly and not hrough a hub.
>USB OTG defines two roles for devices: OTG A-device and OTG B-device, specifying which side supplies power to the link, and which initially is the host. The OTG A-device is a power supplier, and an OTG B-device is a power consumer. In the default link configuration, the A-device acts as a USB host with the B-device acting as a USB peripheral. The host and peripheral modes may be exchanged later by using Host Negotiation Protocol (HNP)
>Eg of OTG version is that of a tablet computer of mobile phone which can have default slave role for a PC or the master role for printer

DATA TRANSFER TYPES: >USB architecture allows four tpes of data transfers: control, interrupt, bulk data, and isochronous >control transfer are used by host computer drivers to configure devices that are attached to the system. The host learns about the peripheral through this transfer. >interrupt transfer are used for data that must be transferred with a limited delay and not stored in buffers >Isochronous Transfer is used where data delivery at constant rate is important even if some data gets missed or corrupted >bulk transfer used with peripherals such as mass storage devices. They have no guaranteed bandwidth. The transfer takes place when there is some bandwidth left after allocating bandwidth to Control, Interrupt and Isochronous transfer. If there is no bandwidth available or the bus is busy, the transfer may take very long to complete.

COMMUNICATION MODEL: (THEH PIC) >Each physical device consists of several logical subdevices called logical functiosn (like speaker and mic). >USB device communicaiton is based on pipes, whcih is a connection from host controller to a logical entity within a device called an endpoint where each endpoints contain input or output buffers through which the communication between the host computer an USB device is achieved. Endpoints are grouped into interfaces and eaech interface is associated with a single device function (excepion of endpoint 0).Lower speed device may contain only two more (beside that 0). Full speed contain maximum 15 besides 0. >Each logical device has unique address, assigned by system when device is attached to the bus. Each endpoint on USB is identified by a unique number, qhich is given at design time. >Each pipe is assigned some information such as requried transfer size, transfer type, and associated endpont’s characteristics such as direction and buffer size. >Two pipe communication modes: stream or message: in stream mode, data has no usb defined structure. data are transferred sequentially and have a predefined direction, input or output. Stream pipes support interrupt, bult data or isochronous. In message moe, is biredirectional, short, simple commands to device and for sttus responses from the device, eg pipe number 0

USB SIGNLS: >To carry signals and supply voltage, USB 2. uses a cable of four wires (pic). >Carries supply voltage for the peripherals on the Vbus which is +5V and GND lines: 0V. Bust terminators are used at each end of the calbe to ensure correct voltage levels, allow to detect detachment and removal of peripheral and to differentiate full speed and low speed perihperals >The differential data signals are transmitted on the D+ and D- lines, consisting of two twisted wires. The encoding method is NRZI (with bit stuffing). Provides syncrhonization field to allowe receivers to synchronize their clocks Differential 1: D+ high, D- low Differential 0: D- high, D+ low Single Ended one: D+ and D- high Single Ended zero: D+ and D- low States: Idle: diff 0, diff 1 Data J: diff 0, diff 1 Data K: diff 1, diff 0 SOP: switching from idle to K state EOF: SE0 for 2 bit times followed by J for 1 bit time (and others)

USB Protocols: >uses a packet based protol, where all transfers are initated by the USB controller of the host computer. Bust transactions invovle the transmission of four packet types: >token packet, data packet, handshake packet, special packet >each transaction starts when USB controller sends, based on shecduing a taken packet that describes the type of transaction its direction, the address of USB device and the endpoint number. The transaction source then sends a data packet contatinig the data to be transfreered or it may indicate that it has no data to send by the fac thtat the data packet does not contain useful information. In generla the destination responds by a handshake packet indicating if the transfer has been completed successfull of if the endpoint is not avaible. Special packets indicate specials.

PACKET FIELDS:
	>SOP:
	>Synchronization field (for all): all packets begins with SYNC field, which is used by receiver circuity for syncrhonization with the transmitter clcok. is 8 bit for low/full speed. Contains 6 successive transision from 1 to 0 or vice versa followed by marker of two bits that is used to identify end of syn field
	>Packet identifier field (for all): PID field immediately follows the syn filed. The PID field contains four its that indivates the packet type followed by four check bist that ensures reliable decoding of PID field. The cehck bit contain the 1's complement of the bits that repsent the paket type. If PID is receied with incorrect check values then assume to be corrupted. the 8-bit side has 2^4 possibility that also defines sub-packety types
	>Address field specififes the address of the USB function that is the source or destination of a data packet. This field is 7bit in length allowing to speicy upto 128 addresses. Each address defines a single funciton. Address 0 is reseved as default addresss and may not be assigned explicity to a funciton. 
	>Endpont field allows more flexible addressing of functions in which several endpoints are required. The filed is 4 bit in length
	>Data field: may ontain zero and 1024 BYTES (8 for low speed) on the transfer type
	>CRC fields: contain cycle reduncance check codes used to verify the intergrity of various fields in the token and data packets
	>EOP: SE0 for 2 bit times followed by J for 1 bit time
	
>TOKEN PACKETS:
	>only sent by host computer, PID can identify whether IN, OUT, SETUP or SOF.
	>IN and OUT subtype inform the USB device on the direction of that follows, input (reading by host computer), or output (writing by the host computer). For a packet IN, ADDR and ENDP fields uniquely identify the endpoint that will receive the next data packet. For a packet OUT, also same. THE CRC5 does for ADDR AND ENDP
	>SETUP is used at the beginning of control transfers. Also identifies as OUT

>(also part of token) For synchronization of the entire USB system, the host computer sends a SOF (start of frame) packet at each and every period corresponding to the beginning of a frame or micro-frame. A frame represents a time interval of 1ms for fullspeed. tHE addr and endp fields are merged into a frame number (has CRC5 or EOP). No handshake needed in return

>Actual information is sent over the bus in data packets. A data packets consists of SYNC, PID, a data field and 16 it CRC with EOP. for low speed 8 bytes, for full speed 1023 bytes4. PID identifies the DATA0, DATA1, DATA2 (for high speed input isochronous) or MDATA (output aschronous)

>Handshake only consists of field SYNC, a packet idnetifier PID and EOP. Report status of a data transaction by the subtype returned in the PID field. Subtypes are: acknowledge (error free), NAK (receiving device cannot accept data or transmitting cannot send), STALL (endpoint is halted), NYET (no response received from the receiver)

DATA ACQUISITION SYSTEM: >Collection of software and hardware that process of sampling signals that measure real world physical conditions and converting the resulting samples into digital numeric values that can be analysed and manuplulated by a computer. Components of data acquisition systems include: 1. Sensors, to convert physical paramters into electrical signals
2. Signal conditioning circuitry, to convert sensor signals into a form that can be convertted to digital values 3. Analog-to-digital converters, to convert conditionaed senro signals to dgiital values >Process: -Begins with the physcial phenomenon or physical property to be measured like temperatures, vibration, light intensity, gas pressure, fluid flow and force which must be converted into a form cam be sampled by data acquisiton sytem through the devices called snesors -Signal conditioning may be necssary if the signal from the transducer is not suitable for the DAQ hardware being used. May need to be amplified, fileered or shaped -For single ended analog signals, which are more susceptible to noise can be converted to differential signals -Once digitalized the signal can be encoded to reduce and correct transmission errors -Eg: IBM 1800 data acquisition and control system

DATA LOGGERS: >A data logger is a self-contained unit that does not require a host to operate which can be installed at almost any location and left to operate unintended. >Automatically makes a record of the readiings of instruments located at different parts of the plant >Measures and record data effortlessly as quicklly, as oftern, and as accurately as desired >Used in power generation plant, petrochemical installations, real time processing palnts, weather station recording, environmental monitoring -Input signals: (high level signals from pressure transducers, low level from thermocouples, digital quantities) -Input scanner: (short operating time, long operation life, negligible contanct bounce) A scanner, in effect, is a multiway switch which is operated by a scanner drive unit for selecting the ciruits. As the scanner select each input signal in turn, data logger operation requires only one signal amplifier and conditioner, one AD converter. Modern sanners have input scanner which can scan at the rate of 150 inputs per seconds but the rate of scnaning has to be matced with the rate of change of input data. Eg: rotary selector switch, electromagnetic operated relays, solid state switches -Signal conditioner (low output impedance, high input impedance, good linearity, high snr, high cmmr) -AD converter (resolution, accuracy, conversion time, linearity..) -Recorder: (speed, memory, writing technique: serial/parallel) The output from the data logger can be printed on any of the following: Typewriter, Strip printer, digital tape recorder, punched tape, computer, magnetic tape etc -Programmer: (not a human operator) Automatic sequence switch which control the sequence operation of the various items of the logger, tells scanner when to step to a new channel and receives information from the scanner, converter and recorder -Real time clock: Tells programmer to seqeunce one set of measurements at intervals selected by the user

Good design begins with grounding and shielding; as properly connected grounds reduce dangerous voltage differentials between instruments while shields minimize interference from noise by reducing noise emissions and noise susceptibility

NOISE PROTECTION: >Noise is undesired electrical and magentic activity that couples one circuit to anotjer >It involves a source, a coupling mechanism and a receiver.

1. The noise sources generate either a periodic signal or a transient pulse that disrupts other ciruits such as power lines, motors, high-voltage equipments (spark plugs, igniters), discharges and sparks (lightning, static electricity), high-current equipment (arc welders)

2. The coupling mechanism can be conductive, thus requiring a closed-circuit loop, inductive such as mutual inductance, capacitive assoicated with high voltage fields; or electromagnetic.

3. The third component is a susceptible receiver. Examples of susceptibility include crosstalk on inputs that lead to bit flips in digital logic, radio interference, and crackle, and static discharge that destroys components. 

>Principle of coupling is that current follows the path of lowest impedance, and not necessarily lowest resistance. Consequently, charge follows the path of minimum inductive and maximum capacitive reactance for the lowest impedance, particularly for frequenceis at or above the audio range (>3kHz)
>For frequencies above 3kHZ, the diagnostic for determining the mechanism is the ratio of rate of change in voltage to the rate of change in current. For special cases of sinusoidal signals or resistive loads, the ratio is impedance; otherwise, it is a pseudo impedance value. A low value (<377ohm) indicates a large change in current and inductive coupling; a high value (>377) indicates a large change in voltage and capacitive coupling. At very high frequencies, a ratio near 377 indicates electromagnetic coupling

1. Conductive:
	-Conductive coupling requires a connection between the source and receiver that completes a continuous circuit that dominates at lower frequencies while at high frequencies, conductive circuit paths can have significant capacitive and inductive properties
	-DC to 10 MHz
	Reasons and solutions:
		i. One reason is due to non perfect resistors (FIG)
		ii. Another is ground loop which allows flow of substantial current in ground path which produces voltages differences across the grounds and raise ground potential at the loads (FIG)
	
2. Capacitive
	-If a conductive wire is too close to the cirucit conductor, it can create the electric field forming a capacitor and this can transfer different types of currents
	-Requires both proximity between circuits and a changing voltage. 
	-Usually > 1KHz
	Reasons and solutions:
		i. Close conductors (FIG)
		ii. No appropriate sheilding (FIG)
		iii. High frequency
	
3. Inductive:
	-Magnetic fields (inductive) generated by the external sources may interfere with the instruments. Also, they can be produced by currents in wires and more strongly by the coils inside the instrument itself, propagating as mutual inductance between circuits
	-The mechanism requires a current loop that generates a changing magnetic flux. Generally current transient creates the magnetic flux. The induced voltage in a coupled circuit is proportional to the rate of cahnge of current and loop area. Since inductance is a function of loop area, reducing the loop area will reduce inductive reactance of a circuit.
	-Usually > 3KHz
	Reasons and solutions:
		i. A slot in the ground plane of a circuit board will increase the loop area of a circuit (FIG)
		ii. Long, straight wires encompass significant loop area that provides an inductive reactance so twist the pair of signal and return lines together to eliminate the loop area and the mutual inductive coupling between circuits (FIG)
		
4. Electromagnetic:
	-Emission sources are usually radio and microwave transmitters and other high frequency circuis. EMI begins as a conductive noise in wires enclosures, becomes radiative and ends as conductive (field interact and cicuitry).
	>Electromagnetic coupling is a high frequency (20MHz) phenomena that requires a transmitting antenna in the source and a receiving antenna in the susceptilbe circuit which antennas must be in appropriate fraction of the signal wavelength to couple effectively
	>Below 200MHz, cables are primary sources and receivers for electromagnetic coupling; above 200MHz, PCB traces begin to radiate and couple energy

	

GROUNDING: >Provides a signal reference (usually the return conductors) with the objective to reduce the voltage difference between the components with respect to a reference point. >Good practice to separate ground for analog and digital circuits >Grounding can be arranged to be single-point grounding if the instrument has a high-impedance ground structure, or multipoint grounding with low-impedance ground structures. (FIG)

>Safety grounding seeks to reduce the voltage differential between exposed conducting surfaces, while signal referencing seeks to reduce voltage reference points. 

>Two return conductor configurations:
	1. Single point grounding: 
		>The separate ground conductors isolate the noise in the return path of separate circuit and eliminate the ground loops betweem circuits.
		>Appropriate for low current and low frequency circuits (less than 1MHz)
		>Eg: ADC (FIG)
		
		Disadvantages:
			-Long conductors are susceptible to high frequency ground noise
	
	2. Multipoint grounding:
		>Preffered at high frequencies (>10MHz)
		>A ground plane is a large area of copper foil on the board which is connected to power supply ground terminal and serves as a return path for current from different components on the board. It has lower impedance than a single cable
		>Eg: Digital devices in which ground planes or grids are used
	
	NOTE: Ground Loop:
		>A complete circuit comprising a signal path and part of the ground structure which arises whenever multiple connections to high impedance ground are physically separated
		>External currents in ground structure generate potential differences between ground connections and introduce noise in the electrical circuit
		>Generally, the problem arises at low frequencies because high frequencies follow the path of minimum impedance that can avoid higher impedance ground loops
	

FILTERING: >Filters are used to remove unwanted parts of a signal where they may be used, for instance, to block undesirable frequencies emitted near a radio receiver (i.e. to reduce radiated radio frequency interference). >A filter can block or pass energy by three criteria: 1. Frequency A low-pass filter passes low-frequency energy and rejects high frequencies, while a high-pass filter passes high-frequency energy and rejects low frequencies. Time average and time-sync filters are frequency selective as well 2. Amplitude An amplitude selective filter generally removes large transients, or spikes of noise energy, from a signal line. Surge suppressors that are built into AC power strips are amplitude-selective filters to protect sensitive equipment 3. Mode Filters diverts common mode into ground passing differntial mode

>Mechanisms of filtering:			
	1. Minimize Bandwidth: (FIG)
		>Harmonic contents of a signal fall on the higher fourier coefficients range hence slowing the rise and fall times of a pulse edge i.e. minimizng bandwidth using low pass filter will reduce the higher frequencies. 
		>E.g. Filtering out clock signal to reduce high frequny harmonics could significantly reduce noise interference.

	2. Ferrite beads:
		>Is a type of choke that suppresses high frequency electronic noise in circuits by employing high frequency current dissipation in ferrite ceramic
		>The geometry and electromagnetic properties of coiled wire over the ferrite bead result in an impedance for high frequency singals attenuating high frquency electronic noise. In contrast, a pure conductor does not dissipate energy but produces reactance that impedes the flow of high frequency signals
		>Used as a passive low pass filter
		>prevents EMI in two directions: from device or to a device. 
		>Large beads are commonly seen on external cabling while various small ferrite beads are used internally in circuits
		
	3. Decoupling capacitors:
		>Makes use of their capacitor characteristics of high impedance in low frequency ranges and low impedance in high frequency ranges. 
		>During a logic transition, a momentary short circuit from power to return in a digital device demands a large current transient. A decoupling capacitor can supply the momentary pulse of current and effectively decoupling the switching spike from the power supply
		>At high frequenceies, the inductive parasitic can become troublesome, resulting in circuit oscillations and ringing. The bypass capacitors are important to elimiante these high frequency oscillations that may be transmitted to other parts of the device.
	
	4. Line filters, isolators, and transient suppressors
		>Line filters and isolators select energy on the basis of mode, while transient suppressors select energy on the basis of amplitude
		>A common-mode filter for AC power lines diverts noise to ground. An optoisolator can eliminate common-mode noise by interrupting the conductive path. 
		>A differential-mode filter has to separate noise from signal by criteria other than current direction; a low-pass LC filter is an example of differential-mode filter that uses frequency as the selection criteria
		>Transient from lightning or machinery protection can take one of four approaches:
			-Filter: removes high frequency components of the energy associated with the sharp edge of a spike
			-Crowbar (Thyristor): detects an overvoltage and short-circuits until the input is cycled off and on again
			-Arcing discharge: occurs across the gap in a gas tube where the initial breakdown of the gas requires fairly high voltage, but once the arc is established the holding voltage is much lower. Used in telephone to suppress surge due to lightning
			-Voltage clamp (Zener diode): shorts the excess energy to prevent an overvoltage condition


	

SHIELDING: >Shield is a barrier enveloping an electrical circuit to provide insulation to suppresses noise energy or perevents it from coupling between circuts. The noise enery can be through magnetic flux, electric field or wave propagation.

1. Electric:
	SOURCES:
	(Same)
	
	HOW?
	-Reduces noise coupling by reducing or rerouting electrical charges in electric field
	-Electric field (capacitive) coupling can effectively be blocked by proper electrostatic shielidng using suitably shaped metals. This is because an electric charge cannot exist on the interior of a closed conductive suraface.
	-Grounding ensures that current from stray capacitance flows to the signal reference ground rather than feed back and causes crosstalk.
	-The effectiveness of shielding can be improved by reducing the noise voltage and frequency and signal impedance at frequencies less than 1MHz

2. Magnetic:
	SOURCES:
	(Same)
	
	HOW?
	-Reduces noise coupling by reducing or rerouting magnetic flux
	-Effective shielding minimizes the loop area and separates the crcuits, also twisting of signal and return conductors minimizes the loop area. Coaxial cables at high frequencies (1Mhz) provide a minimal area because it provides both good capacitive shielding and a controlled impedance. Making sure that return path is always under the signal conductor to minimize loop area. Avoid slots.
	-To provide magnetic shielding, one or more shells of high permeability magnetic materials can be used as enclosures or metal components that surround the parts to be shielded. The ends of each shell are separated by insulations so that shells do not act as single shorted turns. Enclosures provide magnetic shielding by allowing eddy currents to reflect or absorb interference energy
	
3. Electromagnetic:
	-Reduces emission and reception.
	
	HOW?
	-A shielded enclosure should ideally be a completely closed watertight metallic surface. As opening inclduing cooling vents, cable peneterations with slots larger than a fraction of a wavelength (>L/20), pushbottons and monitor screens can leak electromagnetic radiation
	-Reduced bandwidth (longer wavelenths)	
		

AGAINST THE ELECTROSTATIC DISCHARGE: >ESD is a discharge a very high voltage and very low current that readlily damanges sensitive electronics. ESD can range from hundreds to tens of thousands of volts >ESD transfers electrical charge in three stages: pickup, storage, and discharge. Usually mechanical rubbing between dry, insulated materials transfers the charge from source to storage. Often the storage medium is a person, who then unwittingly delivers the discharge. >The discharge waveform of ESD has a fast rise time and short duration >Several schemes, including grounding, shielding, and transient limiters to protect circuits from ESD -Sometimes shielding can be too expensive or cumbersome -Input gates are most susceptible to damage, so you should use surge limiters on input lines (FIG). Most IC incoroporate reverse-based dioded connected between the input and either the ground or the power. These diodes divert high-voltage transients from input gates, but they have a limited current capacity. Generally you can choose between zener diodes and MOV to limit surges. Zener didoes tend to turn faster, while MOVs are cheaper and handle larger peak current -Beyond surge limiters, prevention is the best medicine. Proper handling components will reuce the chance of ESD. Control methods include grounding, protective handling, protective materials, humidity. Checklist to make work areas less prone to ESD 1. Use a static-free workstation, and wear a wrist ground strap 2. Discharge static before handling devices 3. Keep parts in their original containrs 4. Pickup devices by their bodies, not their leads 5. Clear all plastic, vinyl and styrofoam from the work area 6. Never slide a semiconductor over any surface 7. Use conductive or anistatic containers for storage and transport of components

CIRCUIT DESIGN: (Requirements to design, Choose a processor for embedded system, Reliability, Fault tolerance, High speed design, Low power design)

CONVERTING REQUIREMENTS INTO DESIGN:

>Establishing is the most difficult part of circuit design. General-to-specific approach may serve in establishing requirements
1. Start by defining the desired function in broad terms
2. Then refine the function with operational concern through communication with stakeholders
3. Finally settle on exact regulations and specifications
>Setting specifications is one of the most difficult parts of engineering which requires good judgement and experience are necessary to help understand
>The division between solid requirements and design is never sharp because requirements often change late in the effort and spoil the design. Furthermore, the technology interacts with the requirements to mold them		
>Some principles can help bound the design problem. By knowing region of the operation for your system, you will be able to pick the options available for circuit design. Eg. Use of electromagnetic spectrum. 
>Some requirements that drive design:
	1. Function: Response times, Data rates, I/O drive, Reliabiilty-MTBF
	2. Regulations: FCC, UL, Militay regulations
	3. Environment: Volume, Weight, Vibration
	4. Operation: Bandwidth, Speed, Accuracy, Noise, Power consumption
>(FIG) helps to select the appropriate technology and refine the focus of the circuit design. Your time and effort in design increases as the complexity of the function of your system increases
	-An ASIC may solve a signal- or data-processing problem optimally in terms of high throughput and low power, but it will cost more than a collection of standard components

>Further factors that go into selecting a processor for an embedded system:
	-Experience
	-Software and development tools
	-Performance
	-Number of perihperal functions
	-Memory
	-Tool support for particular processor

	1. Performance:
		-Related to architecture of the processor and its processing capacity in bits (4, 8, 16, or 32)
		-Throughput
		-Resolution and dynamic range
		-Address space and available memory
		-Language choice: code size, speed (compilation and actual execution)
		-Predominant types of calculations: integer or floating point
		
		>Resolutions to 0.5% and dynamic ranges of 1 part in 1000 can easly be achieved by an 8-bit microcontroller. In contrast, resolutions of 1 part per mililon, dynamic ranges of 10 parts per billions and high throughput will call for a 32-bit microprocessor with DMA control. The real issue is speed: How much information do you need to process per second? Sure, you could implement 64-bit math on a 4-bit contorller, but it would be very slow.

	2. Peripheral function:
		-Math coprocessors
		-Graphics accelerators
		-Interrupt handlers
		-ADCs, DACs
		-Watchdog timer
		
		>Some microcontrollers integrate some of these functions onto a single chip to reduce the parts count and increase the reliability. 
		
	3. Memory:
		>The architecture of microprocessor does not include memory or peripheral, so you will include these components in your design, thereby increasing the parts count and complexity. Can estimate the amount of memory by adding up the possible sizes of the following:
			-Data arrays
			-Stack
			-Temporary and permanent variables
			-Compiler overhead
			-IO buffers
		>Sum of the estimates will give a minimum size for memory. Always plan and specify margin in your memory requirements. Might need more memory to support new algorithms
	
	4. Power consumption:
		>Power consumption within the processor always play role in systems design either for colling concern or for sizing a battery. Some models dissipate considerably less than others or can be powered down for short periods to reduce the dissipation
	
	5. Experience and tool support
		>What experience do you have, and what tools are available to support your development?
		>Do hardware emulators exist that will help you debug both circuits and code?
		>What software tools are avaialbe to support development on the selected processor? 
		>Does the vendor have good reputation?
		
			

RELIABILITY: >The probability that a component of assembly operates without failure for a prescribed period under specified conditions >Two factors drive reliability: -Complexity: Fewer parts are almost always better -Design margin: Allow for stressing of components >Two methods of measuring reliability: 1. Model prediction Models should be used early to update estimates of reliability; however models are limited and cant predict every outcome 2. Prototype tests Tests of prototypes may find many weaknesses and problems, but they are time consuming >Consequently, you will want to use a combination of model prediction and testing to estimate reliability of your product >The failure rate for a component is generally a base rate that is modified by various factors: Lambda = Lambda_b Pi_c Pi_q Pi_a where, Lambda = failure rate of the component Lambda_b = base failure rate Pi_e = environmental factor Pi_q = quality factor Pi_a = acceleration factor >Reliability of a component is defined as function of failure rate: R(t) = e^{-Lambda t} where, R(t) = reliability Lambda = failure rate t = time >Reliability of a system is the product of all component reliabilities: Rsystem = PI Ri where, Rsystem = reliability of the system Ri = reliability of component i >You can calculate reliability by looking up the appropriate factors for each component and substituting them into the equations >The failure rates relate acceleration factors to temperature, but not its applications might affect reliabilty: -Corrosion, thermal cracks, secondary diffusion, vibration, electro migration >These can drastically alter reliabilty and sill not predicted by standard models

FAULT TOLERANCE: >Property that enables a system to continue operating properly in the event of the failure of one or more faults within some of its components. >Goes beyond the design and analysis for reliable operation and reduces the possibility of dysfunction or damange from abnormal stresses and failures. >Fault tolerance is primarily a philosophy of system design and architecture which has three distinct areas: 1. Careful design Can avoid many failures from abnormal stresses by cconservative and careful design: -Reduce overstress from heat with cooling and lower-dissipation design -Use optoisolation and transformer coupling to stop overvoltage and leakage current -Implement ESD protection -Mount for shock (accidental drops) and vibration -Tie down wires and cables that flex frequently, and use strain relief -Prevent incorrect hookup; use keyed connectors 2. Testable functions >Process of testing and disgnosing failures within a system: >Two possible configurations of testable architecture: 1. Simple Configuration: Provides probe points/test points for a technician or instrument to simulate circuits and record responses. ONly the trained personnel must disassemble the system and remove the circuit for testing 2. Complex Configuration: Dedicated internal circuitry called built int test (BIT) that tests the system and diagnoses problems without disassembly of the equipment so adds complexity and reduces reliability >Regardless of the configuraiton for testing, an appropriate calibration standard is always necessary when you measure a result

	3. Redundant architectures (FIGS)
		>Most complex and fault-tolerant architectures are reduntant systems which use multiple copies and software to self-check between functions.
		>Only justified when downtme for repair and maintenance cannot be tolerated
			1. Doubly redundant architecture
				Merely indicates a failure in one of the subsystems; this allows for quick repair
			2. Triply redundant architecture
				Uses voting between the outputs of three identical modules to select the correct value. It can have a failure and still operate correctly
			3. Dissimal redundance
				Compares the output from modules with different software and hardware to select the correct output. It can survive failure and even indicate errors in design if one system is coded correctly and others are not
		
		

HIGH SPEED DESIGN: >Considerations when clock frequency exceeds 1 MHz in a circuit or system as harmonics generated by the edges of the clock and signal pulses can easily be 20 or 30 times the fundamental >Two conservative criteria may be used to estimate when transmission line effect begins: 1. Circuit dimension vs signal wavelength: If circuit dimensions exceed 5% of the minimum wavelength, then the signal path approaches a transmission line l > Lamda/20 where, l = length of signal path Lambda = maximum wavelength of the signal 2. Rise time vs propagation delay: If the rise time of a signal tr is less thatn four times the propagation delay of the signal path, tp, the the signal path approximates a transmission line with a characteristic impedance: tr < 4tp where, tr = rise time of a signal tp = propagation delay of the signal path >Careful designs solve problems associated with transmission lines that contribute to noise in circuits: -Bandwidth limitation, decoupling, ground bounce, crosstalk, impedance mismatch, and timing skew or delay

1. Bandwidth:
	-Limiting bandwidth of the signals within a system is the most effective way to reduce noise, EMI and problems with transmission lines
		i. May limit bandwidth either by increasing the rise and fall times of the signal edges or by reducing the clock frequency. Slower edge rates allow longer interconnections between circuits
		ii. Selecting appropriate logic family will set the edge rates and the consequent limit on transmission line concerns. One criteria for selecting logic according to transmission line effects is a ratio less than 4 between the rise time, tr, and the propagation delay, tp (tr/tp < 4)

	
2. Decoupling
	-Switching of digital logic causes transients of current on the voltage supply through inductive impedance of the circuit
	-Decoupling capacitor minimizes the inductive loop area thus reducing impedance of power supply circuit
	-Shortest possible path for decoupling capacitor is best
		i. Use decoupling capacitor near each chip for two-sided boards
		ii. Use large filter capacior at the power entry pins
		iii. Use a ferrite bead at the power entry point to the circuit board
	
	
3. Ground Bounce
	-Ground bounce is a voltage surge that couples through the ground leads of a chip into nonswitching output and injects glitches onto signal lines
	-There is a small inductance that leads the package ground to PCB ground, which matters for high switching devices, as a result there exists a possibiilty for the local source and ground of an IC to drift from the actual voltage source and ground of your board caused by the inducance of the contacts
	-Asynchronous signals are more prone to ground bounce
		i. Reduce loop inductance using a bypass capacitor to provide local charge storage for the transistor
		ii. Reducing input gate capacitance
		iii. Choosing logic families that either control the signal transition or have slower fall times
		
4. Crosstalk
	-Coupling electromagnetic energy from an active signal to a passive line
	-Mechanisms are capacitive or inductive
	-Is a function of line spacking, characteristics impedance, and signal rise times
		i. Decreasing the coupling length and characteristics impedance
		ii. Increasing rise times of the signal
		iii. Better layout and design of circuits
		iv. Reduce the length that two lines are allowed to run in parallel- especially for ashynchornous signals

		
GROUND BOUNCE IS EXTREME CASE OF CROSSTALK
	-better layout and design
	-solid return paths where possible
	-use guard traces with vias connected to ground
	-use slow switching signals as possible
		
5. Impedance Matching
	-Impedance matching makes the source and termination impedance equal to the characteristic impedance of the transmission line so that it will eliminate the reflections of signals that cause ringing (oscillations), undershoot, and overshoot in the signal pulses
	-Impedance discontinuities occur in two configurations:
		1. End point discontinuity:
			The end of transmission line dont match its characteristic impedance of the transmission line
				i. Add series resistances at the end until the total impedance equals the line impedance
				ii. Terminate the other end of the signal line from driver
		2. Stub discontinuity:
			Cause impedance mismatch and signal reflection by connecting multiple circuits to a single line
				i. Each connection of a stub divides the impedance and slipts the power of the signal
				ii. Make them very short, even zero to reduce effect of stub discontinuities
				iii. Good layout and design

6. Timing
	-Clock frequency increases propagation delays, timing skew and phase jitter render logic design useless
	-Clock signal is skewed or arrived at different propagation delays of the clock signal to different destinations
	-Differences in propagation delay of rising and falling edges change the duty cycle of the signal or shrink/expand it
	-Adequate setup and hold time is required to latch data reliably
	

LOW POWER DESIGN: >Collection of techniques and methodologies aimed to reducing the overall dynamic and static power consumption of an integrated circuit (IC) >Cellular telephones, TV remote controls, digital multimeters, floating instrumentation for isolation, modems, security systems, video camcorders, and laptop computers are low-power devices >Low power is used for portability, isolation, battery power, and low heat dissipation >Power is a function of frequency, load capacitance, and voltage; reduction in any of these will reduce the consumption of power by your system. This applies to only to complementary CMOS components. P = fCV^2 where, P = power f = frequency C = load capacitance V = DC supply voltage

>Guideliness in design to minimize power:
	1. Lower clock frequency
	2. Lower supply voltage to digital logic
	3. Shut down unused circuits
	4. Put controller into sleep mode when not needed
	5. Terminate all unused inputs. Dont allow any to float as noise will cause the outputs of tates to transition slowly, causing excess current demand that destroys the device
	6. Avoid slow signal transitions. Outputs of gates that transition slowly draw excess current, in CMOS and TTL
	7. Make normal states use the lowest current; for instance, LEDs should be off
	

RESET AND POWER FAILURE DETECTION (FIG) >All systems should initialize to a known state whenever power is applied >Reset circuit generates a signal that prevents the generation of unwanted conditions by the system during power application >Reset signal: -Forces the processor to begine execution from a fixed memory location where code for initializing the system operation is written -Sets or clears critical output signals to states that don’t cause undesirable actions >Reset circuit senses voltage level and generate reset signal when the voltage of power supply goes below the preset values and the reset signal stays active until the voltage of the power supply exceed preset value >Some system may turn on the battery backup after power failure and also inform the processor through interrupt >Eg: RC network, watchdog timer -The simplest reset circuit uses the time constant of the R1C network to set the desired duration of the reset network -Schmitt trigger inverter transforms the exponential charging waveform on the input to a signal transition appropriate for logic gates -Diode allows charge to drain off the capacitor if the DC voltage fails, thereby protecting the inverter from an input voltage higher than its supply volage. -When pressed push botton shorts the charge on the capacitor to ground to generate a reset signal.

INTERFACE UNIT: >Input to all circuits is some sort of electrical signal which comes from another circuit, a transducer, or a switch. >Most signals need preprocessing or conversion before the system can assimilate them 1. Switches generate logic transitions that bounce when pressed; that is there is a series of rapid glitches at the beginning and end of the signal pulse. So necessary to design some circuitry to suppress the glitches produced by bounce 2. Sensors produce continuously changing analog signal that must be converted to digital logic levels for further processing. >Early in development you will need to define the types of inputs that you expect the system will receive. Once you know the type of input, you can decide on the necessary circuitry to manipulate the input signals

CIRCUIT LAYOUT

CIRCUIT BOARDS: >Circuit boards combine electronic components and connectors into a functional system through electrical connections and mechanical support. >Different configurations:

	1. Wire wrap
		-Electronic components mounted on an insulating board are interconnected by lengths of insulated wire run between their terminals, with the connections made by wrapping several turns of uninsulated sections of the wire around a component lead or a socket pin
		-Suitable for prototype development as you can easily change the connections
		-Circuit modifications and corrections are straightforward
		-Requires extensive effort
		-Limited in operations to less thatn 5 or 10 MHz, above which the loop inductances in the wired connections distort signals
	
	2. Stitch weld
		-Connects components with point to point wiring on circuit boards much like wire wrap
		-Stitch weld posts are shorter and the wire is welded to the pins, not wrapped; therefore loop inductances are lower and allow much higher speed operation (100MHz) 
		-Resists vibration and shock better than wire wrap and has been used in spacecraft
		-More expensive and requires a special welding station


	3. PCB
		-PCB is a non-conductive material with conductive lines printed where electronic components are mounted on the board and the traces connect the components together to from a working circuitry or assembly
		-PCBs make automated placement and soldering of components possible, and they control impedances more effectively than wire wrap
		-Contain layers of insulating material and copper conductors with plated holes called vias, to interconnect the conductors
		
		1. Single sided PCBs
			-A single-sided PCB is a type of PCB where the components and conductive copper are mounted on one side and the conductive wiring is on the other side
			-Circuit realization using a single sided PCB consumes a lot of space and is suitable for low-density circuit designs
			-Still used in products like audio amplifiers because it is cheap and can operate satisfactorliy in low frequencies (typically less than 25 KHz)
			-Cost is low because production of PCB has few steps; only one side needs etching, and plating is not necessary
			
		2. Double sided PCBs
			-Has signal traces on both sides of the circuit board and plated-through vias.
			-Double-sided PCBs are best for realizing high density circuits that do not require point-to-point soldering.
			-Can support higher frequency operation if laid out very carefully
			-Higher cost of manufacturing
			
		
		3. Multi layer PCB:
			-Is a stack of alternating layers of copper-clad laminate, or core, and prepreg
			-Supports very dense circuit connections as they can have 20 or 30 conducting layers laminated together
			-Controls impedance much more tightly than double-sided PCBs
			-Absolute necessary for high frequency circuits
			-Through-hole, buried and blind vias connect signals paths on different layers together
				>Through hole vias penerate all layers and can connect signals on each layer
				>Buried vias connect traces on two sides of an internal layer
				>Blind vias is exposed on one external layer and connects traces on the two sides of it

	4. Hybrid and MCM
		-An electronic assembly where multiple integrated circuits and/or other discrete components are integrated, usually onto a unifying substrate, so that in use it can be treated as if it were a larger IC
		-Higher level of circuit density by bonding the base die of ICs onto a substrate
		-Compact packing improves signal speeds and reduces load capacitance
		-Expensive to fabriacte, but recent advances in materials and processing are now making MCMs cost-effective in some products

COMPONENT PLACEMENT: (FIG) >For the best PCB performance, components need to be placed where they will best serve the functional needs of the circuitry >Placement of components affects circuit operation, manufacturign ease, and the probability of design errors where the improper layout can degrade operation or even precent a circuit from working. Thoughtless placement of components complicates the design of the PCB and will increase the chance of wrong connections >Guideliness 1. Group high current circuits near the connector to isolate stray currents and near the edge of the PCB to remove heat 2. Group high frequency circuits near the connector to reduce path length, crosstalk and noise 3. Group low power and low frequency circuits away from high current and high frequency circuits 4. Group analog circuits separately from digital logic

ROUTING SIGNAL TRACES: >A signal trace or circuit trace on a printed circuit board is the equivalent of a wire for condcuting singals where each trace consits of a flat, narrow part of the copper foil that remains after etching >Problems such as false triggering of logic, setup and hold violations, and transmission delays- arise from poor layout. Bad techniques cause these problems by forming capacitive and inductive parasitics with stubs, vias, IC pins, multiple loads, and traces

1. Trace Density
	As you squeeze traces together on a board, you can space components closer and reduce the size of circuit boards. Smaller boards, allowed by higher trace densities, provide flexibility in packing product and may reduce the cost of materials. The trade off, however, is greater cost and difficult in producing the denser circuit boards. Furthermore, higher trace densities may degrade signal integrity

2. Avoiding crosstalk
	To reduce cross talk:
		i. Dont run parallel traces for long distances- particularly asynchronous signals
		ii. Increase separation between conductors
		iii. Shield clock lines with guard strips
		iv. Reduce magnetic coupling by reducing the loop area of circuits
		v. Sandwich signal lines between return planes to reduce crosstalk
		vi. Isolate the clock, chip-select, chip-enable, read and write lines because crosstalk occurs in synchronous systems on the pulse edges when data are sampled
	>Guideliness can run counter to high trace density, so balance noise, EMI and trace density	

3. Trace impedance and matching
	Impedance of signal conductors directly affects circuit operation
	Low characteristic impedance (Z0) radiates less and is less susceptible to interference thatn a circuit with higher impedance
	Impedance mismatches lead to reflections that can both delay switching and trigger logic falsely
	Tailor both the dielectric constant of the PCB materials and the packing between signal traces and the return plane to match impedance and reduce radiation and susceptibility
	Terminate signal trace appropriately
	Multiple loads have stubs, nonuniform impedances, and mismatches that compromise noise margins and can cause inadvertent switching. Careful layout of the signal path can improve the situation by eliminating stubs	
	
4. Common impedance
	Minimize the number of circuits that share the same return path. Voltage drops (caused by current switching) on the ground line (return path) increases system noise. Common impedance paths cause components to reside at different ground potentials from one another
	Reduce voltage drops, and hence noise by lowering effective impedance
	Unbroken return plane (without slots) is the best way
	Choosing the right logic family and using decoupling capacitors will help by reducing the magnitude of current pulses

5. Distribution of signals and return
	Address the issues of reutrn path early in design
	Long return path can shift the ground potential excessively, decrease the noise margins, and can cause false switching
	If the return is longer than signal, then the current has high inductance path that causes noise spikes in the ground system
	Large loops of current have high impedance and radiated noise is oftern proportional to return path impedance and loop area
	
6. Transmission line concerns
	Signal conductors are never ideal transmission lines
	Characteristics impedance: Depends on frequency; higher frequencies attenuate more than lower frequencies
	Dispersion: Signals at different frequencies propagate at different speeds
	Propagation delay: Can corrupt circuit operation; depends on interconnection length and signal velocity
	Line resistance, skin effect and dielectric losses: Degrade signals and introduce delay and errors into circuit operation
	

GROUNDS, RETURNS, AND SHIELDS >A proper ground and return scheme will shield and suppress most EMI in electronics and reduce errors caused by noise >Provides signal reference which should be a single point and is as close as possible to power entry to the PCB >A ground plane connected to the single-point reference will also reduce common impedance >Be sure to separate the analog and digital circuits so that current pulses from digital circuits will not corrupt sensitive analog circuits >Use common ground plane or different planes and connect their ground leads to the single-point reference

>A return plane is the most effective shield for any circuit
>Power and return planes provide circuit paths with the lowest impedance, which reduces radiation, noise and crosstalk.
>Minimizing spacing between power and return will minimize impedance (radiation and susceptibility)

CABLES AND CONNECTORS >